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AMDGPU: Set DX10Clamp bit 

llvm-svn: 259088
This commit is contained in:
Matt Arsenault 2016-01-28 20:53:35 +00:00
parent 6b52052f33
commit 7293f9895e
2 changed files with 12 additions and 3 deletions
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5
llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
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@ -476,11 +476,10 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
// register.
ProgInfo.FloatMode = getFPMode(MF);
// XXX: Not quite sure what this does, but sc seems to unset this.
ProgInfo.IEEEMode = 0;
// Do not clamp NAN to 0.
ProgInfo.DX10Clamp = 0;
// Make clamp modifier on NaN input returns 0.
ProgInfo.DX10Clamp = 1;
const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
ProgInfo.ScratchSize = FrameInfo->estimateStackSize(MF);

10
llvm/test/CodeGen/AMDGPU/hsa-fp-mode.ll Normal file
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@ -0,0 +1,10 @@
; RUN: llc -march=amdgcn -mcpu=kaveri -mtriple=amdgcn-unknown-amdhsa -mattr=-fp32-denormals,+fp64-denormals < %s | FileCheck -check-prefix=FP64-DENORMAL -check-prefix=COMMON %s
; COMMON-LABEL: {{^}}test_kernel:
; COMMON-DENORMAL: compute_pgm_rsrc1_float_mode = compute_pgm_rsrc1_float_mode = 192
; COMMON-DENORMAL: compute_pgm_rsrc1_dx10_clamp = 1
define void @test_kernel(float addrspace(1)* %out0, double addrspace(1)* %out1) nounwind {
store float 0.0, float addrspace(1)* %out0
store double 0.0, double addrspace(1)* %out1
ret void
}