forked from OSchip/llvm-project
Support Custom lowering of a few more operations.
Alpha needs to custom lower *DIV and *REM llvm-svn: 25006
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@ -537,6 +537,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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case ISD::GlobalAddress:
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case ISD::TargetGlobalAddress:
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case ISD::ExternalSymbol:
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case ISD::TargetExternalSymbol:
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case ISD::ConstantPool: // Nothing to do.
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case ISD::BasicBlock:
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case ISD::CONDCODE:
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@ -1954,9 +1955,25 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Tmp2 = PromoteOp(Node->getOperand(1)); // Promote the RHS.
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break;
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}
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if (Tmp1 != Node->getOperand(0) ||
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Tmp2 != Node->getOperand(1))
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Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
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switch (TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0))) {
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case TargetLowering::Legal:
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if (Tmp1 != Node->getOperand(0) ||
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Tmp2 != Node->getOperand(1))
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Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1,Tmp2);
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break;
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case TargetLowering::Custom: {
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Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2);
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SDOperand Tmp = TLI.LowerOperation(Result, DAG);
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if (Tmp.Val) {
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Tmp = LegalizeOp(Tmp); // Relegalize input.
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AddLegalizedOperand(Op, Tmp);
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return Tmp;
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}
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break;
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}
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default:
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assert(0 && "Operation not supported");
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}
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break;
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case ISD::BUILD_PAIR: {
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@ -1997,8 +2014,17 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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Tmp2);
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break;
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case TargetLowering::Promote:
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case TargetLowering::Custom:
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assert(0 && "Cannot promote/custom handle this yet!");
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assert(0 && "Cannot promote handle this yet!");
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case TargetLowering::Custom: {
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Result = DAG.getNode(Node->getOpcode(), Node->getValueType(0), Tmp1, Tmp2);
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SDOperand Tmp = TLI.LowerOperation(Result, DAG);
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if (Tmp.Val) {
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Tmp = LegalizeOp(Tmp); // Relegalize input.
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AddLegalizedOperand(Op, Tmp);
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return Tmp;
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}
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break;
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}
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case TargetLowering::Expand:
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if (MVT::isInteger(Node->getValueType(0))) {
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MVT::ValueType VT = Node->getValueType(0);
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