forked from OSchip/llvm-project
[SparcInstPrinter] Use the subtarget that is passed to the print function
instead of the one passed to the constructor. Unfortunately, I don't have a test case for this change. In order to test my change, I will have to run the code after line 90 in printSparcAliasInstr. I couldn't make that happen because printAliasInstr would always handle the printing of fcmp instructions that the code after line 90 is supposed to handle. llvm-svn: 233471
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28f550b4df
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@ -34,7 +34,7 @@ namespace Sparc {
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#define PRINT_ALIAS_INSTR
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#include "SparcGenAsmWriter.inc"
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bool SparcInstPrinter::isV9() const {
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bool SparcInstPrinter::isV9(const MCSubtargetInfo &STI) const {
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return (STI.getFeatureBits() & Sparc::FeatureV9) != 0;
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}
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@ -45,13 +45,14 @@ void SparcInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const
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void SparcInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
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StringRef Annot, const MCSubtargetInfo &STI) {
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if (!printAliasInstr(MI, O) && !printSparcAliasInstr(MI, O))
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printInstruction(MI, O);
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if (!printAliasInstr(MI, STI, O) && !printSparcAliasInstr(MI, STI, O))
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printInstruction(MI, STI, O);
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printAnnotation(O, Annot);
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}
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bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, raw_ostream &O)
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{
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bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI,
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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switch (MI->getOpcode()) {
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default: return false;
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case SP::JMPLrr:
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@ -71,16 +72,16 @@ bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, raw_ostream &O)
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case SP::O7: O << "\tretl"; return true;
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}
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}
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O << "\tjmp "; printMemOperand(MI, 1, O);
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O << "\tjmp "; printMemOperand(MI, 1, STI, O);
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return true;
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case SP::O7: // call $addr
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O << "\tcall "; printMemOperand(MI, 1, O);
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O << "\tcall "; printMemOperand(MI, 1, STI, O);
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return true;
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}
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}
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case SP::V9FCMPS: case SP::V9FCMPD: case SP::V9FCMPQ:
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case SP::V9FCMPES: case SP::V9FCMPED: case SP::V9FCMPEQ: {
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if (isV9()
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if (isV9(STI)
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|| (MI->getNumOperands() != 3)
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|| (!MI->getOperand(0).isReg())
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|| (MI->getOperand(0).getReg() != SP::FCC0))
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@ -95,17 +96,17 @@ bool SparcInstPrinter::printSparcAliasInstr(const MCInst *MI, raw_ostream &O)
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case SP::V9FCMPED: O << "\tfcmped "; break;
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case SP::V9FCMPEQ: O << "\tfcmpeq "; break;
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}
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printOperand(MI, 1, O);
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printOperand(MI, 1, STI, O);
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O << ", ";
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printOperand(MI, 2, O);
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printOperand(MI, 2, STI, O);
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return true;
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}
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}
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}
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void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
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raw_ostream &O)
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{
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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const MCOperand &MO = MI->getOperand (opNum);
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if (MO.isReg()) {
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@ -123,14 +124,14 @@ void SparcInstPrinter::printOperand(const MCInst *MI, int opNum,
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}
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void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum,
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raw_ostream &O, const char *Modifier)
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{
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printOperand(MI, opNum, O);
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const MCSubtargetInfo &STI,
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raw_ostream &O, const char *Modifier) {
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printOperand(MI, opNum, STI, O);
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// If this is an ADD operand, emit it like normal operands.
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if (Modifier && !strcmp(Modifier, "arith")) {
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O << ", ";
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printOperand(MI, opNum+1, O);
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printOperand(MI, opNum+1, STI, O);
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return;
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}
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const MCOperand &MO = MI->getOperand(opNum+1);
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@ -142,12 +143,12 @@ void SparcInstPrinter::printMemOperand(const MCInst *MI, int opNum,
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O << "+";
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printOperand(MI, opNum+1, O);
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printOperand(MI, opNum+1, STI, O);
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}
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void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
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raw_ostream &O)
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{
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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int CC = (int)MI->getOperand(opNum).getImm();
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switch (MI->getOpcode()) {
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default: break;
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@ -170,8 +171,8 @@ void SparcInstPrinter::printCCOperand(const MCInst *MI, int opNum,
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}
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bool SparcInstPrinter::printGetPCX(const MCInst *MI, unsigned opNum,
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raw_ostream &O)
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{
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const MCSubtargetInfo &STI,
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raw_ostream &O) {
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llvm_unreachable("FIXME: Implement SparcInstPrinter::printGetPCX.");
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return true;
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}
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@ -22,33 +22,38 @@ namespace llvm {
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class MCOperand;
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class SparcInstPrinter : public MCInstPrinter {
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const MCSubtargetInfo &STI;
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public:
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SparcInstPrinter(const MCAsmInfo &MAI,
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const MCInstrInfo &MII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &sti)
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: MCInstPrinter(MAI, MII, MRI), STI(sti) {}
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: MCInstPrinter(MAI, MII, MRI) {}
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void printRegName(raw_ostream &OS, unsigned RegNo) const override;
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void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
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const MCSubtargetInfo &STI) override;
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bool printSparcAliasInstr(const MCInst *MI, raw_ostream &OS);
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bool isV9() const;
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bool printSparcAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
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raw_ostream &OS);
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bool isV9(const MCSubtargetInfo &STI) const;
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// Autogenerated by tblgen.
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void printInstruction(const MCInst *MI, raw_ostream &O);
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bool printAliasInstr(const MCInst *MI, raw_ostream &O);
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void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
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raw_ostream &O);
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bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
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raw_ostream &O);
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void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
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unsigned PrintMethodIdx, raw_ostream &O);
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unsigned PrintMethodIdx,
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const MCSubtargetInfo &STI, raw_ostream &O);
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static const char *getRegisterName(unsigned RegNo);
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void printOperand(const MCInst *MI, int opNum, raw_ostream &OS);
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void printMemOperand(const MCInst *MI, int opNum, raw_ostream &OS,
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const char *Modifier = nullptr);
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void printCCOperand(const MCInst *MI, int opNum, raw_ostream &OS);
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bool printGetPCX(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
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void printOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
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raw_ostream &OS);
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void printMemOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
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raw_ostream &OS, const char *Modifier = nullptr);
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void printCCOperand(const MCInst *MI, int opNum, const MCSubtargetInfo &STI,
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raw_ostream &OS);
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bool printGetPCX(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
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raw_ostream &OS);
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};
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} // end namespace llvm
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@ -92,8 +92,15 @@ def : Proc<"niagara4", [FeatureV9, FeatureV8Deprecated, UsePopc,
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// Declare the target which we are implementing
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//===----------------------------------------------------------------------===//
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def SparcAsmWriter : AsmWriter {
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string AsmWriterClassName = "InstPrinter";
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int PassSubtarget = 1;
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int Variant = 0;
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}
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def Sparc : Target {
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// Pull in Instruction Info:
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let InstructionSet = SparcInstrInfo;
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let AssemblyParsers = [SparcAsmParser];
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let AssemblyWriters = [SparcAsmWriter];
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}
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