forked from OSchip/llvm-project
[ARM] Make sure that the constant pool does not keep in the middle of an IT block.
This change make sure that llvm does not emit an invalid IT block by putting the constant pool in the middle of an IT block. We have code to try to avoid putting a constant island in the middle of an IT block, but it only works if we see an IT between the one currently referencing CPE and possible insertion point. If the first instruction we look at is the VLDRD after the IT , we never see the IT and does not realize that the instruction doing the load could be in an IT block itself. Differential Revision: https://reviews.llvm.org/D64621 Change-Id: I24cecb37cded75e8992870bd997f6226853bd920 llvm-svn: 366905
This commit is contained in:
Simi Pallipurath
parent
a19f5a76e6
commit
724888af45
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@ -1337,6 +1337,28 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
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BaseInsertOffset =
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std::max(UserBBI.postOffset() - UPad - 8,
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UserOffset + TII->getInstSizeInBytes(*UserMI) + 1);
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// If the CP is referenced(ie, UserOffset) is in first four instructions
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// after IT, this recalculated BaseInsertOffset could be in the middle of
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// an IT block. If it is, change the BaseInsertOffset to just after the
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// IT block. This still make the CP Entry is in range becuase of the
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// following reasons.
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// 1. The initial BaseseInsertOffset calculated is (UserOffset +
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// U.getMaxDisp() - UPad).
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// 2. An IT block is only at most 4 instructions plus the "it" itself (18
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// bytes).
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// 3. All the relevant instructions support much larger Maximum
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// displacement.
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MachineBasicBlock::iterator I = UserMI;
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++I;
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for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI),
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PredReg = 0;
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I->getOpcode() != ARM::t2IT &&
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getITInstrPredicate(*I, PredReg) != ARMCC::AL;
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Offset += TII->getInstSizeInBytes(*I), I = std::next(I)) {
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BaseInsertOffset =
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std::max(BaseInsertOffset, Offset + TII->getInstSizeInBytes(*I) + 1);
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assert(I != UserMBB->end() && "Fell off end of block");
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}
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LLVM_DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));
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}
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unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad +
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@ -1397,9 +1419,10 @@ void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
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}
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// We really must not split an IT block.
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LLVM_DEBUG(unsigned PredReg; assert(
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!isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL));
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#ifndef NDEBUG
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unsigned PredReg;
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assert(!isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL);
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#endif
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NewMBB = splitBlockBeforeInstr(&*MI);
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}
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@ -0,0 +1,107 @@
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# RUN: llc -run-pass=arm-cp-islands %s -o - | FileCheck %s
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# This test make sure that the constant pool does not keep in the middle of an IT block
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# when needs to split a block to place them.
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#
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--- |
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; ModuleID = '<stdin>'
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source_filename = "<stdin>"
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target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8m.main-arm-none-eabi"
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%struct.e = type { double, double, double }
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declare i32 @llvm.arm.space(i32, i32)
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define hidden arm_aapcs_vfpcc %struct.e @h() {
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unreachable
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}
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...
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---
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name: h
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alignment: 2
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers: []
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liveins: []
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 64
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offsetAdjustment: -40
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maxAlignment: 4
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adjustsStack: true
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hasCalls: true
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maxCallFrameSize: 0
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 28
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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callSites: []
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constants:
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- id: 0
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value: 'double 0.000000e+00'
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alignment: 8
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isTargetSpecific: false
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- id: 1
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value: 'double 7.020000e+02'
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alignment: 8
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isTargetSpecific: false
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- id: 2
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value: 'double 2.020000e+02'
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alignment: 8
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isTargetSpecific: false
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machineFunctionInfo: {}
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body: |
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bb.0:
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successors: %bb.1(0x80000000)
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renamable $d0 = VLDRD %const.0, 0, 14, $noreg :: (load 8 from constant-pool)
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dead renamable $r0 = SPACE 40, undef renamable $r0
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bb.1:
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successors: %bb.2(0x80000000)
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dead renamable $r0 = SPACE 790, undef renamable $r0
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bb.2:
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successors:
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renamable $r0 = t2MOVi 0, 14, _, _
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t2CMPri $r0, 32, 14, $noreg, implicit-def $cpsr
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renamable $r0 = SPACE 200, undef renamable $r0
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; CHECK: t2IT 0, 1, implicit-def $itstate
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; CHECK-NEXT: renamable $d0 = VLDRD %const.7, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool)
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; CHECK-NEXT: renamable $d1 = VLDRD %const.5, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool)
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; CHECK-NEXT: renamable $d2 = VLDRD %const.6, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool)
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; CHECK-NEXT: $r0 = t2SUBri $r0, 12, 0, $cpsr, $noreg, implicit killed $itstate
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t2IT 0, 1, implicit-def $itstate
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renamable $d0 = VLDRD %const.1, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool)
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renamable $d1 = VLDRD %const.2, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool)
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renamable $d2 = VLDRD %const.0, 0, 0, $cpsr, implicit $itstate :: (load 8 from constant-pool)
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$r0 = t2SUBri $r0, 12, 0, $cpsr, $noreg, implicit killed $itstate
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t2IT 0, 4, implicit-def $itstate
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$sp = tMOVr $r0, 0, $cpsr, implicit $itstate
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$sp = t2LDMIA_RET $sp, 0, killed $cpsr, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $r11, def $pc, implicit killed $d0, implicit killed $d1, implicit killed $d2, implicit $sp, implicit killed $itstate
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tBL 14, $noreg, &__stack_chk_fail, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
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bb.3:
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successors: %bb.3(0x80000000)
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liveins: $r0
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dead renamable $r0 = SPACE 4000, undef renamable $r0
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t2B %bb.3, 14, $noreg
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