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[ARM] GlobalISel: Lower single precision FP args 

Both for aapcscc and aapcs_vfpcc. We currently filter out soft float targets
because we don't support libcalls yet.

llvm-svn: 294584
This commit is contained in:
Diana Picus 2017-02-09 13:09:59 +00:00
parent 75dcfe8449
commit 7232af352f
3 changed files with 79 additions and 4 deletions
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10
llvm/lib/Target/ARM/ARMCallLowering.cpp
View File

@ -35,7 +35,7 @@ ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI)
static bool isSupportedType(const DataLayout &DL, const ARMTargetLowering &TLI,
Type *T) {
EVT VT = TLI.getValueType(DL, T, true);
if (!VT.isSimple() || !VT.isInteger() || VT.isVector())
if (!VT.isSimple() || VT.isVector())
return false;
unsigned VTSize = VT.getSimpleVT().getSizeInBits();
@ -205,7 +205,13 @@ bool ARMCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
auto DL = MF.getDataLayout();
auto &TLI = *getTLI<ARMTargetLowering>();
if (TLI.getSubtarget()->isThumb())
auto Subtarget = TLI.getSubtarget();
if (Subtarget->isThumb())
return false;
// FIXME: Support soft float (when we're ready to generate libcalls)
if (Subtarget->useSoftFloat() || !Subtarget->hasVFP2())
return false;
auto &Args = F.getArgumentList();

50
llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -mtriple arm-unknown -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
; RUN: llc -mtriple arm-unknown -mattr=+vfp2 -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
define void @test_void_return() {
; CHECK-LABEL: name: test_void_return
@ -172,3 +172,51 @@ entry:
%v = load i32, i32* %p
ret i32 %v
}
define arm_aapcscc float @test_float_aapcscc(float %p0, float %p1, float %p2,
float %p3, float %p4, float %p5) {
; CHECK-LABEL: name: test_float_aapcscc
; CHECK: fixedStack:
; CHECK-DAG: id: [[P4:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
; CHECK-DAG: id: [[P5:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4
; CHECK: liveins: %r0, %r1, %r2, %r3
; CHECK: [[VREGP1:%[0-9]+]](s32) = COPY %r1
; CHECK: [[FIP5:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[P5]]
; CHECK: [[VREGP5:%[0-9]+]](s32) = G_LOAD [[FIP5]](p0)
; CHECK: [[VREGV:%[0-9]+]](s32) = G_FADD [[VREGP1]], [[VREGP5]]
; CHECK: %r0 = COPY [[VREGV]]
; CHECK: BX_RET 14, _, implicit %r0
entry:
%v = fadd float %p1, %p5
ret float %v
}
define arm_aapcs_vfpcc float @test_float_vfpcc(float %p0, float %p1, float %p2,
float %p3, float %p4, float %p5,
float %ridiculous,
float %number,
float %of,
float %parameters,
float %that,
float %should,
float %never,
float %exist,
float %in,
float %practice,
float %q0, float %q1) {
; CHECK-LABEL: name: test_float_vfpcc
; CHECK: fixedStack:
; CHECK-DAG: id: [[Q0:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4
; CHECK-DAG: id: [[Q1:[0-9]+]]{{.*}}offset: 4{{.*}}size: 4
; CHECK: liveins: %s0, %s1, %s2, %s3, %s4, %s5, %s6, %s7, %s8, %s9, %s10, %s11, %s12, %s13, %s14, %s15
; CHECK: [[VREGP1:%[0-9]+]](s32) = COPY %s1
; CHECK: [[FIQ1:%[0-9]+]](p0) = G_FRAME_INDEX %fixed-stack.[[Q1]]
; CHECK: [[VREGQ1:%[0-9]+]](s32) = G_LOAD [[FIQ1]](p0)
; CHECK: [[VREGV:%[0-9]+]](s32) = G_FADD [[VREGP1]], [[VREGQ1]]
; CHECK: %s0 = COPY [[VREGV]]
; CHECK: BX_RET 14, _, implicit %s0
entry:
%v = fadd float %p1, %q1
ret float %v
}

23
llvm/test/CodeGen/ARM/GlobalISel/arm-isel.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -mtriple arm-unknown -global-isel %s -o - | FileCheck %s
; RUN: llc -mtriple arm-unknown -mattr=+vfp2 -global-isel %s -o - | FileCheck %s
define void @test_void_return() {
; CHECK-LABEL: test_void_return:
@ -139,3 +139,24 @@ entry:
%v = load i8*, i8** %p
ret i8* %v
}
define arm_aapcs_vfpcc float @test_float_hard(float %f0, float %f1) {
; CHECK-LABEL: test_float_hard:
; CHECK: vadd.f32 s0, s0, s1
; CHECK: bx lr
entry:
%v = fadd float %f0, %f1
ret float %v
}
define arm_aapcscc float @test_float_softfp(float %f0, float %f1) {
; CHECK-LABEL: test_float_softfp:
; CHECK-DAG: vmov [[F0:s[0-9]+]], r0
; CHECK-DAG: vmov [[F1:s[0-9]+]], r1
; CHECK: vadd.f32 [[FV:s[0-9]+]], [[F0]], [[F1]]
; CHECK: vmov r0, [[FV]]
; CHECK: bx lr
entry:
%v = fadd float %f0, %f1
ret float %v
}