From 72281a228b77796a07f0314c4f0ce081119319f1 Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Thu, 7 Dec 2017 11:05:38 +0000 Subject: [PATCH] [RISCV] Add missed tests for RV64D MC layer support Add tests missed in r320029. llvm-svn: 320031 --- llvm/test/MC/RISCV/rv64d-invalid.s | 11 +++++++ llvm/test/MC/RISCV/rv64d-valid.s | 49 ++++++++++++++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 llvm/test/MC/RISCV/rv64d-invalid.s create mode 100644 llvm/test/MC/RISCV/rv64d-valid.s diff --git a/llvm/test/MC/RISCV/rv64d-invalid.s b/llvm/test/MC/RISCV/rv64d-invalid.s new file mode 100644 index 000000000000..0f508aafd9be --- /dev/null +++ b/llvm/test/MC/RISCV/rv64d-invalid.s @@ -0,0 +1,11 @@ +# RUN: not llvm-mc -triple riscv64 -mattr=+d < %s 2>&1 | FileCheck %s + +# Integer registers where FP regs are expected +fcvt.l.d ft0, a0 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction +fcvt.lu.d ft1, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction +fmv.x.d ft2, a2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction + +# FP registers where integer regs are expected +fcvt.d.l a3, ft3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction +fcvt.d.lu a4, ft4 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction +fmv.d.x a5, ft5 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction diff --git a/llvm/test/MC/RISCV/rv64d-valid.s b/llvm/test/MC/RISCV/rv64d-valid.s new file mode 100644 index 000000000000..e24fd250d43a --- /dev/null +++ b/llvm/test/MC/RISCV/rv64d-valid.s @@ -0,0 +1,49 @@ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+d -show-encoding \ +# RUN: | FileCheck -check-prefixes=CHECK,CHECK-INST %s +# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+d < %s \ +# RUN: | llvm-objdump -mattr=+d -d - | FileCheck -check-prefix=CHECK-INST %s +# RUN: not llvm-mc -triple riscv32 -mattr=+d < %s 2>&1 \ +# RUN: | FileCheck -check-prefix=CHECK-RV32 %s + +# CHECK-INST: fcvt.l.d a0, ft0 +# CHECK: encoding: [0x53,0x75,0x20,0xc2] +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.l.d a0, ft0 +# CHECK-INST: fcvt.lu.d a1, ft1 +# CHECK: encoding: [0xd3,0xf5,0x30,0xc2] +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.lu.d a1, ft1 +# CHECK-INST: fmv.x.d a2, ft2 +# CHECK: encoding: [0x53,0x06,0x01,0xe2] +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fmv.x.d a2, ft2 +# CHECK-INST: fcvt.d.l ft3, a3 +# CHECK: encoding: [0xd3,0xf1,0x26,0xd2] +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.d.l ft3, a3 +# CHECK-INST: fcvt.d.lu ft4, a4 +# CHECK: encoding: [0x53,0x72,0x37,0xd2] +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.d.lu ft4, a4 +# CHECK-INST: fmv.d.x ft5, a5 +# CHECK: encoding: [0xd3,0x82,0x07,0xf2] +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fmv.d.x ft5, a5 + +# Rounding modes +# CHECK-INST: fcvt.d.l ft3, a3, rne +# CHECK: encoding: [0xd3,0x81,0x26,0xd2] +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.d.l ft3, a3, rne +# CHECK-INST: fcvt.d.lu ft4, a4, rtz +# CHECK: encoding: [0x53,0x12,0x37,0xd2] +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.d.lu ft4, a4, rtz +# CHECK-INST: fcvt.l.d a0, ft0, rdn +# CHECK: encoding: [0x53,0x25,0x20,0xc2] +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.l.d a0, ft0, rdn +# CHECK-INST: fcvt.lu.d a1, ft1, rup +# CHECK: encoding: [0xd3,0xb5,0x30,0xc2] +# CHECK-RV32: :[[@LINE+1]]:1: error: instruction use requires an option to be enabled +fcvt.lu.d a1, ft1, rup