forked from OSchip/llvm-project
Major enhancements to how array and structure indices are handled.
Improve checking for constants in Multiply. Simpler method to keep track of when a node is folded into its parent. Several other bug fixes. llvm-svn: 1964
This commit is contained in:
Vikram S. Adve
parent
650ad5e881
commit
72213c9a66
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@ -37,7 +37,7 @@ static void SetMemOperands_Internal (vector<MachineInstr*>& mvec,
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vector<MachineInstr*>::iterator mvecI,
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const InstructionNode* vmInstrNode,
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Value* ptrVal,
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const std::vector<Value*>& idxVec,
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std::vector<Value*>& idxVec,
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const TargetMachine& target);
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@ -263,9 +263,11 @@ ChooseConvertToFloatInstr(const InstructionNode* instrNode,
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// This is usually used in conjunction with CreateCodeToCopyIntToFloat().
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// Both functions should treat the integer as a 32-bit value for types
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// of 4 bytes or less, and as a 64-bit value otherwise.
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if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
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if (opType == Type::SByteTy || opType == Type::UByteTy ||
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opType == Type::ShortTy || opType == Type::UShortTy ||
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opType == Type::IntTy || opType == Type::UIntTy)
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opCode = FITOD;
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else if (opType == Type::LongTy)
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else if (opType == Type::LongTy || opType == Type::ULongTy)
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opCode = FXTOD;
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else if (opType == Type::FloatTy)
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opCode = FSTOD;
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@ -505,18 +507,22 @@ CreateIntNegInstruction(const TargetMachine& target,
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// Does not create any instructions if we cannot exploit constant to
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// create a cheaper instruction
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static inline void
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// create a cheaper instruction.
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// This returns the approximate cost of the instructions generated,
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// which is used to pick the cheapest when both operands are constant.
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static inline unsigned int
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CreateMulConstInstruction(const TargetMachine &target,
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Value* lval, Value* rval, Value* destVal,
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vector<MachineInstr*>& mvec)
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{
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/* An integer multiply is generally more costly than FP multiply */
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unsigned int cost = target.getInstrInfo().minLatency(MULX);
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MachineInstr* minstr1 = NULL;
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MachineInstr* minstr2 = NULL;
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Value* constOp = rval;
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if (! isa<Constant>(constOp))
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return;
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return cost;
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// Cases worth optimizing are:
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// (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV)
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@ -540,29 +546,31 @@ CreateMulConstInstruction(const TargetMachine &target,
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if (C == 0 || C == 1)
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{
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cost = target.getInstrInfo().minLatency(ADD);
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minstr1 = new MachineInstr(ADD);
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if (C == 0)
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minstr1->SetMachineOperandReg(0,
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target.getRegInfo().getZeroRegNum());
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else
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minstr1->SetMachineOperandVal(0,MachineOperand::MO_VirtualRegister,
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lval);
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minstr1->SetMachineOperandReg(1,target.getRegInfo().getZeroRegNum());
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minstr1->SetMachineOperandVal(0,
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MachineOperand::MO_VirtualRegister, lval);
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minstr1->SetMachineOperandReg(1,
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target.getRegInfo().getZeroRegNum());
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}
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else if (IsPowerOf2(C, pow))
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{
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minstr1 = new MachineInstr((resultType == Type::LongTy)
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? SLLX : SLL);
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minstr1->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
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lval);
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minstr1->SetMachineOperandConst(1, MachineOperand::MO_UnextendedImmed,
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pow);
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minstr1->SetMachineOperandVal(0,
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MachineOperand::MO_VirtualRegister, lval);
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minstr1->SetMachineOperandConst(1,
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MachineOperand::MO_UnextendedImmed, pow);
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}
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if (minstr1 && needNeg)
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{ // insert <reg = SUB 0, reg> after the instr to flip the sign
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minstr2 = CreateIntNegInstruction(target, destVal);
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cost += target.getInstrInfo().minLatency(minstr2->getOpCode());
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}
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}
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}
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@ -593,12 +601,53 @@ CreateMulConstInstruction(const TargetMachine &target,
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destVal);
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if (minstr1)
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{
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mvec.push_back(minstr1);
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cost = target.getInstrInfo().minLatency(minstr1->getOpCode());
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}
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if (minstr2)
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{
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assert(minstr1 && "Otherwise cost needs to be initialized to 0");
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cost += target.getInstrInfo().minLatency(minstr2->getOpCode());
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mvec.push_back(minstr2);
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}
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return cost;
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}
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// Does not create any instructions if we cannot exploit constant to
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// create a cheaper instruction.
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//
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static inline void
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CreateCheapestMulConstInstruction(const TargetMachine &target,
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Value* lval, Value* rval, Value* destVal,
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vector<MachineInstr*>& mvec)
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{
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Value* constOp;
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if (isa<Constant>(lval) && isa<Constant>(rval))
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{ // both operands are constant: try both orders!
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vector<MachineInstr*> mvec1, mvec2;
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unsigned int lcost = CreateMulConstInstruction(target, lval, rval,
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destVal, mvec1);
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unsigned int rcost = CreateMulConstInstruction(target, rval, lval,
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destVal, mvec2);
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vector<MachineInstr*>& mincostMvec = (lcost <= rcost)? mvec1 : mvec2;
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vector<MachineInstr*>& maxcostMvec = (lcost <= rcost)? mvec2 : mvec1;
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mvec.insert(mvec.end(), mincostMvec.begin(), mincostMvec.end());
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for (unsigned int i=0; i < maxcostMvec.size(); ++i)
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delete maxcostMvec[i];
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}
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else if (isa<Constant>(rval)) // rval is constant, but not lval
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CreateMulConstInstruction(target, lval, rval, destVal, mvec);
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else if (isa<Constant>(lval)) // lval is constant, but not rval
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CreateMulConstInstruction(target, lval, rval, destVal, mvec);
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// else neither is constant
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return;
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}
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// Return NULL if we cannot exploit constant to create a cheaper instruction
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static inline void
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CreateMulInstruction(const TargetMachine &target,
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@ -607,7 +656,7 @@ CreateMulInstruction(const TargetMachine &target,
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MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE)
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{
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unsigned int L = mvec.size();
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CreateMulConstInstruction(target, lval, rval, destVal, mvec);
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CreateCheapestMulConstInstruction(target, lval, rval, destVal, mvec);
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if (mvec.size() == L)
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{ // no instructions were added so create MUL reg, reg, reg.
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// Use FSMULD if both operands are actually floats cast to doubles.
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@ -686,9 +735,11 @@ CreateDivConstInstruction(TargetMachine &target,
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if (C == 1)
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{
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minstr1 = new MachineInstr(ADD);
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minstr1->SetMachineOperandVal(0,MachineOperand::MO_VirtualRegister,
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minstr1->SetMachineOperandVal(0,
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MachineOperand::MO_VirtualRegister,
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instrNode->leftChild()->getValue());
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minstr1->SetMachineOperandReg(1,target.getRegInfo().getZeroRegNum());
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minstr1->SetMachineOperandReg(1,
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target.getRegInfo().getZeroRegNum());
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}
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else if (IsPowerOf2(C, pow))
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{
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@ -696,9 +747,11 @@ CreateDivConstInstruction(TargetMachine &target,
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? (resultType==Type::LongTy)? SRAX : SRA
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: (resultType==Type::LongTy)? SRLX : SRL);
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minstr1 = new MachineInstr(opCode);
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minstr1->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
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minstr1->SetMachineOperandVal(0,
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MachineOperand::MO_VirtualRegister,
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instrNode->leftChild()->getValue());
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minstr1->SetMachineOperandConst(1, MachineOperand::MO_UnextendedImmed,
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minstr1->SetMachineOperandConst(1,
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MachineOperand::MO_UnextendedImmed,
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pow);
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}
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@ -724,7 +777,8 @@ CreateDivConstInstruction(TargetMachine &target,
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: (resultType == Type::FloatTy? FMOVS : FMOVD);
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minstr1 = new MachineInstr(opCode);
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minstr1->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
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minstr1->SetMachineOperandVal(0,
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MachineOperand::MO_VirtualRegister,
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instrNode->leftChild()->getValue());
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}
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}
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@ -798,14 +852,17 @@ CreateCodeForFixedSizeAlloca(const TargetMachine& target,
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unsigned int numElements,
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vector<MachineInstr*>& getMvec)
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{
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assert(result && result->getParent() && "Result value is not part of a method?");
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assert(result && result->getParent() &&
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"Result value is not part of a method?");
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Method* method = result->getParent()->getParent();
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MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(method);
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// Check if the offset would small enough to use as an immediate in load/stores
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// (check LDX because all load/stores have the same-size immediate field).
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// If not, put the variable in the dynamically sized area of the frame.
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unsigned int paddedSizeIgnored;
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int offsetFromFP = mcInfo.computeOffsetforLocalVar(target, result,
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paddedSizeIgnored,
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tsize * numElements);
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if (! target.getInstrInfo().constantFitsInImmedField(LDX, offsetFromFP))
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{
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@ -872,21 +929,15 @@ SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
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? vmInstrNode->rightChild()
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: vmInstrNode->leftChild());
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// We can only fold a chain of GetElemPtr instructions for structure references
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// Fold chains of GetElemPtr instructions for structure references.
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//
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if (isa<StructType>(cast<PointerType>(ptrVal->getType())->getElementType())
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&& (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
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ptrChild->getOpLabel() == GetElemPtrIdx))
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{
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// There is a GetElemPtr instruction and there may be a chain of
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// more than one. Use the pointer value of the last one in the chain.
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// Fold the index vectors from the entire chain and from the mem
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// instruction into one single index vector.
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//
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ptrVal = FoldGetElemChain((InstructionNode*) ptrChild, idxVec);
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assert (! cast<PointerType>(ptrVal->getType())->getElementType()->isArrayType()
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&& "GetElemPtr cannot be folded into array refs in selection");
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Value* newPtr = FoldGetElemChain((InstructionNode*) ptrChild, idxVec);
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if (newPtr)
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ptrVal = newPtr;
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}
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// Append the index vector of this instruction (may be none) to the indexes
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@ -905,7 +956,7 @@ SetMemOperands_Internal(vector<MachineInstr*>& mvec,
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vector<MachineInstr*>::iterator mvecI,
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const InstructionNode* vmInstrNode,
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Value* ptrVal,
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const vector<Value*>& idxVec,
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vector<Value*>& idxVec,
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const TargetMachine& target)
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{
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MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
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@ -924,35 +975,54 @@ SetMemOperands_Internal(vector<MachineInstr*>& mvec,
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const PointerType* ptrType = cast<PointerType>(ptrVal->getType());
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if (ptrType->getElementType()->isStructType())
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// Handle special common case of leading [0] index.
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bool firstIndexIsZero =
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bool(isa<ConstantUInt>(idxVec.front()) &&
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cast<ConstantUInt>(idxVec.front())->getValue() == 0);
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// This is a real structure reference if the ptr target is a
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// structure type, and the first offset is [0] (eliminate that offset).
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if (firstIndexIsZero && ptrType->getElementType()->isStructType())
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{
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// Compute the offset value using the index vector,
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// and create a virtual register for it.
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// Compute the offset value using the index vector. Create a
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// virtual reg. for it since it may not fit in the immed field.
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assert(idxVec.size() >= 2);
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idxVec.erase(idxVec.begin());
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unsigned offset = target.DataLayout.getIndexedOffset(ptrType,idxVec);
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valueForRegOffset = ConstantSInt::get(Type::IntTy, offset);
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}
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else
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{
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// It must be an array ref. Check that the indexing has been
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// lowered to a single offset.
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// It is an array ref, and must have been lowered to a single offset.
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assert((memInst->getNumOperands()
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== (unsigned) 1 + memInst->getFirstIndexOperandNumber())
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&& "Array refs must be lowered before Instruction Selection");
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Value* arrayOffsetVal = * memInst->idx_begin();
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// Generate a MUL instruction to compute address from index
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// The call to getTypeSize() will fail if size is not constant
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// If index is 0, the offset value is just 0. Otherwise,
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// generate a MUL instruction to compute address from index.
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// The call to getTypeSize() will fail if size is not constant.
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// CreateMulInstruction() folds constants intelligently enough.
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//
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if (firstIndexIsZero)
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{
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offsetOpType = MachineOperand::MO_SignExtendedImmed;
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smallConstOffset = 0;
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}
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else
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{
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vector<MachineInstr*> mulVec;
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Instruction* addr = new TmpInstruction(Type::UIntTy, memInst);
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MachineCodeForInstruction::get(memInst).addTemp(addr);
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unsigned int eltSize =
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target.DataLayout.getTypeSize(ptrType->getElementType());
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assert(eltSize > 0 && "Invalid or non-constant array element size");
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assert(eltSize > 0 && "Invalid or non-const array element size");
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ConstantUInt* eltVal = ConstantUInt::get(Type::UIntTy, eltSize);
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CreateMulInstruction(target,
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arrayOffsetVal, /* lval, not likely constant */
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arrayOffsetVal, /* lval, not likely const */
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eltVal, /* rval, likely constant */
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addr, /* result*/
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mulVec, INVALID_MACHINE_OPCODE);
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@ -960,25 +1030,12 @@ SetMemOperands_Internal(vector<MachineInstr*>& mvec,
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for (vector<MachineInstr*>::const_iterator I = mulVec.begin();
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I != mulVec.end(); ++I)
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{
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mvecI = mvec.insert(mvecI, *I); // get ptr to inserted value
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++mvecI; // get ptr to mem. instr.
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mvecI = mvec.insert(mvecI, *I); // ptr to inserted value
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++mvecI; // ptr to mem. instr.
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}
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valueForRegOffset = addr;
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// Check if the offset is a constant,
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// if (Constant *CPV = dyn_cast<Constant>(arrayOffsetVal))
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// {
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// isConstantOffset = true; // always constant for structs
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// assert(arrayOffsetVal->getType()->isIntegral());
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// offset = (CPV->getType()->isSigned()
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// ? cast<ConstantSInt>(CPV)->getValue()
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// : (int64_t) cast<ConstantUInt>(CPV)->getValue());
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// }
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// else
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// {
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// valueForRegOffset = arrayOffsetVal;
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// }
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}
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}
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}
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else
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@ -1125,7 +1182,8 @@ CreateCopyInstructionsByType(const TargetMachine& target,
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{ // `src' is constant and cannot fit in immed field for the ADD
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// Insert instructions to "load" the constant into a register
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vector<TmpInstruction*> tempVec;
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target.getInstrInfo().CreateCodeToLoadConst(method, src, dest,minstrVec,tempVec);
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target.getInstrInfo().CreateCodeToLoadConst(method, src, dest,
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minstrVec,tempVec);
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for (unsigned i=0; i < tempVec.size(); i++)
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MachineCodeForInstruction::get(dest).addTemp(tempVec[i]);
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}
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@ -1196,8 +1254,8 @@ GetInstructionsForProlog(BasicBlock* entryBB,
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else
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{
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M = new MachineInstr(SETSW);
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M->SetMachineOperandReg(0, MachineOperand::MO_SignExtendedImmed,
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- staticStackSize);
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M->SetMachineOperandConst(0, MachineOperand::MO_SignExtendedImmed,
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- (int) staticStackSize);
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M->SetMachineOperandReg(1, MachineOperand::MO_MachineRegister,
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target.getRegInfo().getUnifiedRegNum(
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target.getRegInfo().getRegClassIDOfType(Type::IntTy),
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@ -1297,6 +1355,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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mvec.clear();
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// If the code for this instruction was folded into the parent (user),
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// then do nothing!
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if (subtreeRoot->isFoldedIntoParent())
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return;
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//
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// Let's check for chain rules outside the switch so that we don't have
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// to duplicate the list of chain rule production numbers here again
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@ -1383,13 +1446,19 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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&& GetConstantValueAsSignedInt(constVal, isValidConst) == 0
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&& isValidConst)
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{
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BranchInst* brInst=cast<BranchInst>(subtreeRoot->getInstruction());
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// That constant is a zero after all...
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// Use the left child of setCC as the first argument!
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// Mark the setCC node so that no code is generated for it.
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InstructionNode* setCCNode = (InstructionNode*)
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subtreeRoot->leftChild();
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assert(setCCNode->getOpLabel() == SetCCOp);
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setCCNode->markFoldedIntoParent();
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BranchInst* brInst=cast<BranchInst>(subtreeRoot->getInstruction());
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M = new MachineInstr(ChooseBprInstruction(subtreeRoot));
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M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
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subtreeRoot->leftChild()->leftChild()->getValue());
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setCCNode->leftChild()->getValue());
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M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
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brInst->getSuccessor(0));
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mvec.push_back(M);
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@ -1832,34 +1901,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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break;
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case 41: // boolconst: SetCC(reg, Constant)
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// Check if this is an integer comparison, and
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// there is a parent, and the parent decided to use
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// a branch-on-integer-register instead of branch-on-condition-code.
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// If so, the SUBcc instruction is not required.
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// (However, we must still check for constants to be loaded from
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// the constant pool so that such a load can be associated with
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// this instruction.)
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//
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// Otherwise this is just the same as case 42, so just fall through.
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// If the SetCC was folded into the user (parent), it will be
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// caught above. All other cases are the same as case 42,
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// so just fall through.
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//
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if ((subtreeRoot->leftChild()->getValue()->getType()->isIntegral() ||
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subtreeRoot->leftChild()->getValue()->getType()->isPointerType())
|
||||
&& subtreeRoot->parent() != NULL)
|
||||
{
|
||||
InstructionNode* parent = (InstructionNode*) subtreeRoot->parent();
|
||||
assert(parent->getNodeType() == InstrTreeNode::NTInstructionNode);
|
||||
const MachineCodeForInstruction &minstrVec =
|
||||
MachineCodeForInstruction::get(parent->getInstruction());
|
||||
MachineOpCode parentOpCode;
|
||||
if (parent->getInstruction()->getOpcode() == Instruction::Br &&
|
||||
(parentOpCode = minstrVec[0]->getOpCode()) >= BRZ &&
|
||||
parentOpCode <= BRGEZ)
|
||||
{
|
||||
break; // don't forward the operand!
|
||||
}
|
||||
}
|
||||
// ELSE FALL THROUGH
|
||||
|
||||
case 42: // bool: SetCC(reg, reg):
|
||||
{
|
||||
// This generates a SUBCC instruction, putting the difference in
|
||||
|
|
@ -1987,38 +2033,18 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
|||
|
||||
case 55: // reg: GetElemPtr(reg)
|
||||
case 56: // reg: GetElemPtrIdx(reg,reg)
|
||||
if (subtreeRoot->parent() != NULL)
|
||||
{
|
||||
// If the parent was a memory operation and not an array access,
|
||||
// the parent will fold this instruction in so generate nothing.
|
||||
//
|
||||
Instruction* parent =
|
||||
cast<Instruction>(subtreeRoot->parent()->getValue());
|
||||
if (parent->getOpcode() == Instruction::Load ||
|
||||
parent->getOpcode() == Instruction::Store ||
|
||||
parent->getOpcode() == Instruction::GetElementPtr)
|
||||
{
|
||||
// Check if the parent is an array access,
|
||||
// If so, we still need to generate this instruction.
|
||||
GetElementPtrInst* getElemInst =
|
||||
cast<GetElementPtrInst>(subtreeRoot->getInstruction());
|
||||
const PointerType* ptrType =
|
||||
cast<PointerType>(getElemInst->getPointerOperand()->getType());
|
||||
if (! ptrType->getElementType()->isArrayType())
|
||||
{// we don't need a separate instr
|
||||
break; // don't forward operand!
|
||||
}
|
||||
}
|
||||
}
|
||||
// else in all other cases we need to a separate ADD instruction
|
||||
// If the GetElemPtr was folded into the user (parent), it will be
|
||||
// caught above. For other cases, we have to compute the address.
|
||||
mvec.push_back(new MachineInstr(ADD));
|
||||
SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
|
||||
break;
|
||||
|
||||
case 57: // reg: Alloca: Implement as 1 instruction:
|
||||
{ // add %fp, offsetFromFP -> result
|
||||
AllocationInst* instr = cast<AllocationInst>(subtreeRoot->getInstruction());
|
||||
unsigned int tsize =target.findOptimalStorageSize(instr->getAllocatedType());
|
||||
AllocationInst* instr =
|
||||
cast<AllocationInst>(subtreeRoot->getInstruction());
|
||||
unsigned int tsize =
|
||||
target.findOptimalStorageSize(instr->getAllocatedType());
|
||||
assert(tsize != 0);
|
||||
CreateCodeForFixedSizeAlloca(target, instr, tsize, 1, mvec);
|
||||
break;
|
||||
|
|
@ -2028,18 +2054,26 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
|
|||
// mul num, typeSz -> tmp
|
||||
// sub %sp, tmp -> %sp
|
||||
{ // add %sp, frameSizeBelowDynamicArea -> result
|
||||
AllocationInst* instr = cast<AllocationInst>(subtreeRoot->getInstruction());
|
||||
AllocationInst* instr =
|
||||
cast<AllocationInst>(subtreeRoot->getInstruction());
|
||||
const Type* eltType = instr->getAllocatedType();
|
||||
|
||||
// If the #elements is a constant, use simpler code for fixed-size allocas
|
||||
// If #elements is constant, use simpler code for fixed-size allocas
|
||||
int tsize = (int) target.findOptimalStorageSize(eltType);
|
||||
if (isa<Constant>(instr->getArraySize()))
|
||||
// total size is constant: generate code for fixed-size alloca
|
||||
Value* numElementsVal = NULL;
|
||||
bool isArray = instr->isArrayAllocation();
|
||||
|
||||
if (!isArray ||
|
||||
isa<Constant>(numElementsVal = instr->getArraySize()))
|
||||
{ // total size is constant: generate code for fixed-size alloca
|
||||
unsigned int numElements = isArray?
|
||||
cast<ConstantUInt>(numElementsVal)->getValue() : 1;
|
||||
CreateCodeForFixedSizeAlloca(target, instr, tsize,
|
||||
cast<ConstantUInt>(instr->getArraySize())->getValue(), mvec);
|
||||
numElements, mvec);
|
||||
}
|
||||
else // total size is not constant.
|
||||
CreateCodeForVariableSizeAlloca(target, instr, tsize,
|
||||
instr->getArraySize(), mvec);
|
||||
numElementsVal, mvec);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue