maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

Fix another batch of VLD/VST decoding crashes discovered by randomized testing. 

llvm-svn: 138255
This commit is contained in:
Owen Anderson 2011-08-22 18:42:13 +00:00
parent 1d887499c4
commit 721c3704da
2 changed files with 42 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

56
llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
View File

@ -2769,8 +2769,11 @@ static DecodeStatus DecodeVLD1LN(llvm::MCInst &Inst, unsigned Insn,
}
CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF && Rm != 0xD) {
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
if (Rm != 0xF) {
if (Rm != 0xD)
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
else
Inst.addOperand(MCOperand::CreateReg(0));
}
CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@ -2819,8 +2822,11 @@ static DecodeStatus DecodeVST1LN(llvm::MCInst &Inst, unsigned Insn,
}
CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF && Rm != 0xD) {
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
if (Rm != 0xF) {
if (Rm != 0xD)
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
else
Inst.addOperand(MCOperand::CreateReg(0));
}
CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@ -2876,8 +2882,11 @@ static DecodeStatus DecodeVLD2LN(llvm::MCInst &Inst, unsigned Insn,
}
CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF && Rm != 0xD) {
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
if (Rm != 0xF) {
if (Rm != 0xD)
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
else
Inst.addOperand(MCOperand::CreateReg(0));
}
CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@ -2931,8 +2940,11 @@ static DecodeStatus DecodeVST2LN(llvm::MCInst &Inst, unsigned Insn,
}
CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF && Rm != 0xD) {
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
if (Rm != 0xF) {
if (Rm != 0xD)
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
else
Inst.addOperand(MCOperand::CreateReg(0));
}
CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@ -2989,8 +3001,11 @@ static DecodeStatus DecodeVLD3LN(llvm::MCInst &Inst, unsigned Insn,
}
CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF && Rm != 0xD) {
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
if (Rm != 0xF) {
if (Rm != 0xD)
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
else
Inst.addOperand(MCOperand::CreateReg(0));
}
CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@ -3043,8 +3058,11 @@ static DecodeStatus DecodeVST3LN(llvm::MCInst &Inst, unsigned Insn,
}
CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF && Rm != 0xD) {
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
if (Rm != 0xF) {
if (Rm != 0xD)
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
else
Inst.addOperand(MCOperand::CreateReg(0));
}
CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@ -3103,8 +3121,11 @@ static DecodeStatus DecodeVLD4LN(llvm::MCInst &Inst, unsigned Insn,
}
CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF && Rm != 0xD) {
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
if (Rm != 0xF) {
if (Rm != 0xD)
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
else
Inst.addOperand(MCOperand::CreateReg(0));
}
CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));
@ -3158,8 +3179,11 @@ static DecodeStatus DecodeVST4LN(llvm::MCInst &Inst, unsigned Insn,
}
CHECK(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder));
Inst.addOperand(MCOperand::CreateImm(align));
if (Rm != 0xF && Rm != 0xD) {
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
if (Rm != 0xF) {
if (Rm != 0xD)
CHECK(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder));
else
Inst.addOperand(MCOperand::CreateReg(0));
}
CHECK(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder));

2
llvm/test/MC/Disassembler/ARM/neon.txt
View File

@ -1848,4 +1848,6 @@
0x0 0xc 0xa0 0xf4
# CHECK: vld1.8 {d0[]}, [r0], r0
0x0d 0x03 0x80 0xf4
# CHECK: vst4.8 {d0[0], d1[0], d2[0], d3[0]}, [r0]!