forked from OSchip/llvm-project
[X86][SSE] Add ISD::ROTR support
Fix issue in TargetLowering::expandROT where we only attempt to flip a rotation if the other direction has better support - this matches TargetLowering::expandFunnelShift This allows us to enable ISD::ROTR lowering on SSE targets, which particularly simplifies/improves codegen for splat amount and AVX2 per-element shifts.
This commit is contained in:
Simon Pilgrim
parent
0ff20f2f44
commit
71fc4bbdd2
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@ -6657,9 +6657,10 @@ SDValue TargetLowering::expandROT(SDNode *Node, bool AllowVectorOps,
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EVT ShVT = Op1.getValueType();
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SDValue Zero = DAG.getConstant(0, DL, ShVT);
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// If a rotate in the other direction is supported, use it.
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// If a rotate in the other direction is more supported, use it.
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unsigned RevRot = IsLeft ? ISD::ROTR : ISD::ROTL;
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if (isOperationLegalOrCustom(RevRot, VT) && isPowerOf2_32(EltSizeInBits)) {
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if (!isOperationLegalOrCustom(Node->getOpcode(), VT) &&
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isOperationLegalOrCustom(RevRot, VT) && isPowerOf2_32(EltSizeInBits)) {
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SDValue Sub = DAG.getNode(ISD::SUB, DL, ShVT, Zero, Op1);
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return DAG.getNode(RevRot, DL, VT, Op0, Sub);
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}
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@ -1091,12 +1091,11 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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if (VT == MVT::v2i64) continue;
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setOperationAction(ISD::ROTL, VT, Custom);
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setOperationAction(ISD::ROTR, VT, Custom);
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}
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setOperationAction(ISD::ROTL, MVT::v4i32, Custom);
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setOperationAction(ISD::ROTL, MVT::v8i16, Custom);
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setOperationAction(ISD::ROTL, MVT::v16i8, Custom);
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setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
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setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
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setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
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@ -1194,8 +1193,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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if (!Subtarget.useSoftFloat() && Subtarget.hasXOP()) {
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for (auto VT : { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64,
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MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 })
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MVT::v32i8, MVT::v16i16, MVT::v8i32, MVT::v4i64 }) {
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setOperationAction(ISD::ROTL, VT, Custom);
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setOperationAction(ISD::ROTR, VT, Custom);
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}
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// XOP can efficiently perform BITREVERSE with VPPERM.
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for (auto VT : { MVT::i8, MVT::i16, MVT::i32, MVT::i64 })
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@ -1278,6 +1279,9 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::SRL, VT, Custom);
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setOperationAction(ISD::SHL, VT, Custom);
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setOperationAction(ISD::SRA, VT, Custom);
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if (VT == MVT::v4i64) continue;
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setOperationAction(ISD::ROTL, VT, Custom);
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setOperationAction(ISD::ROTR, VT, Custom);
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}
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// These types need custom splitting if their input is a 128-bit vector.
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@ -1286,10 +1290,6 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setOperationAction(ISD::ZERO_EXTEND, MVT::v8i64, Custom);
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setOperationAction(ISD::ZERO_EXTEND, MVT::v16i32, Custom);
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setOperationAction(ISD::ROTL, MVT::v8i32, Custom);
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setOperationAction(ISD::ROTL, MVT::v16i16, Custom);
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setOperationAction(ISD::ROTL, MVT::v32i8, Custom);
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setOperationAction(ISD::SELECT, MVT::v4f64, Custom);
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setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
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setOperationAction(ISD::SELECT, MVT::v8i32, Custom);
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@ -1675,10 +1675,13 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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}
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// With BWI, expanding (and promoting the shifts) is the better.
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if (!Subtarget.useBWIRegs())
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if (!Subtarget.useBWIRegs()) {
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setOperationAction(ISD::ROTL, MVT::v32i16, Custom);
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setOperationAction(ISD::ROTR, MVT::v32i16, Custom);
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}
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setOperationAction(ISD::ROTL, MVT::v64i8, Custom);
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setOperationAction(ISD::ROTR, MVT::v64i8, Custom);
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for (auto VT : { MVT::v64i8, MVT::v32i16 }) {
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setOperationAction(ISD::ABS, VT, HasBWI ? Legal : Custom);
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@ -29847,7 +29850,19 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
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return DAG.getNode(FunnelOpc, DL, VT, R, R, Amt);
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}
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assert(IsROTL && "Only ROTL supported");
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SDValue Z = DAG.getConstant(0, DL, VT);
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if (!IsROTL) {
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// If the ISD::ROTR amount is constant, we're always better converting to
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// ISD::ROTL.
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if (SDValue NegAmt = DAG.FoldConstantArithmetic(ISD::SUB, DL, VT, {Z, Amt}))
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return DAG.getNode(ISD::ROTL, DL, VT, R, NegAmt);
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// XOP targets always prefers ISD::ROTL.
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if (Subtarget.hasXOP())
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return DAG.getNode(ISD::ROTL, DL, VT, R,
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DAG.getNode(ISD::SUB, DL, VT, Z, Amt));
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}
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// Split 256-bit integers on XOP/pre-AVX2 targets.
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if (VT.is256BitVector() && (Subtarget.hasXOP() || !Subtarget.hasAVX2()))
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@ -29857,6 +29872,7 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
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// +ve/-ve Amt = rotate left/right - just need to handle ISD::ROTL.
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// XOP implicitly uses modulo rotation amounts.
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if (Subtarget.hasXOP()) {
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assert(IsROTL && "Only ROTL expected");
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assert(VT.is128BitVector() && "Only rotate 128-bit vectors!");
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// Attempt to rotate by immediate.
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@ -29885,20 +29901,11 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
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(VT == MVT::v64i8 && Subtarget.useBWIRegs())) &&
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"Only vXi32/vXi16/vXi8 vector rotates supported");
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// Check for a hidden ISD::ROTR, splat + vXi8 lowering can handle both, but we
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// currently hit infinite loops in legalization if we allow ISD::ROTR.
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// FIXME: Infinite ROTL<->ROTR legalization in TargetLowering::expandROT.
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SDValue HiddenROTRAmt;
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if (Amt.getOpcode() == ISD::SUB &&
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ISD::isBuildVectorAllZeros(Amt.getOperand(0).getNode()))
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HiddenROTRAmt = Amt.getOperand(1);
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MVT ExtSVT = MVT::getIntegerVT(2 * EltSizeInBits);
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MVT ExtVT = MVT::getVectorVT(ExtSVT, NumElts / 2);
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SDValue AmtMask = DAG.getConstant(EltSizeInBits - 1, DL, VT);
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SDValue AmtMod = DAG.getNode(ISD::AND, DL, VT,
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HiddenROTRAmt ? HiddenROTRAmt : Amt, AmtMask);
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SDValue AmtMod = DAG.getNode(ISD::AND, DL, VT, Amt, AmtMask);
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// Attempt to fold as unpack(x,x) << zext(splat(y)):
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// rotl(x,y) -> (unpack(x,x) << (y & (bw-1))) >> bw.
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@ -29906,7 +29913,7 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
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// TODO: Handle vXi16 cases.
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if (EltSizeInBits == 8 || EltSizeInBits == 32) {
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if (SDValue BaseRotAmt = DAG.getSplatValue(AmtMod)) {
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unsigned ShiftX86Opc = HiddenROTRAmt ? X86ISD::VSRLI : X86ISD::VSHLI;
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unsigned ShiftX86Opc = IsROTL ? X86ISD::VSHLI : X86ISD::VSRLI;
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SDValue Lo = DAG.getBitcast(ExtVT, getUnpackl(DAG, DL, VT, R, R));
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SDValue Hi = DAG.getBitcast(ExtVT, getUnpackh(DAG, DL, VT, R, R));
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BaseRotAmt = DAG.getZExtOrTrunc(BaseRotAmt, DL, MVT::i32);
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@ -29914,7 +29921,7 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
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Subtarget, DAG);
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Hi = getTargetVShiftNode(ShiftX86Opc, DL, ExtVT, Hi, BaseRotAmt,
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Subtarget, DAG);
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return getPack(DAG, Subtarget, DL, VT, Lo, Hi, !HiddenROTRAmt);
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return getPack(DAG, Subtarget, DL, VT, Lo, Hi, IsROTL);
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}
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}
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@ -29925,7 +29932,7 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
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bool IsConstAmt = ISD::isBuildVectorOfConstantSDNodes(Amt.getNode());
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MVT WideVT =
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MVT::getVectorVT(Subtarget.hasBWI() ? MVT::i16 : MVT::i32, NumElts);
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unsigned ShiftOpc = HiddenROTRAmt ? ISD::SRL : ISD::SHL;
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unsigned ShiftOpc = IsROTL ? ISD::SHL : ISD::SRL;
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// Attempt to fold as:
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// rotl(x,y) -> (((aext(x) << bw) | zext(x)) << (y & (bw-1))) >> bw.
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@ -29942,7 +29949,7 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
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getTargetVShiftByConstNode(X86ISD::VSHLI, DL, WideVT, R, 8, DAG));
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Amt = DAG.getNode(ISD::ZERO_EXTEND, DL, WideVT, AmtMod);
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R = DAG.getNode(ShiftOpc, DL, WideVT, R, Amt);
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if (!HiddenROTRAmt)
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if (IsROTL)
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R = getTargetVShiftByConstNode(X86ISD::VSRLI, DL, WideVT, R, 8, DAG);
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return DAG.getNode(ISD::TRUNCATE, DL, VT, R);
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}
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@ -29952,14 +29959,13 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
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// rotr(x,y) -> (unpack(x,x) >> (y & (bw-1))).
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if (IsConstAmt || supportedVectorVarShift(ExtVT, Subtarget, ShiftOpc)) {
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// See if we can perform this by unpacking to lo/hi vXi16.
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SDValue Z = DAG.getConstant(0, DL, VT);
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SDValue RLo = DAG.getBitcast(ExtVT, getUnpackl(DAG, DL, VT, R, R));
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SDValue RHi = DAG.getBitcast(ExtVT, getUnpackh(DAG, DL, VT, R, R));
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SDValue ALo = DAG.getBitcast(ExtVT, getUnpackl(DAG, DL, VT, AmtMod, Z));
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SDValue AHi = DAG.getBitcast(ExtVT, getUnpackh(DAG, DL, VT, AmtMod, Z));
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SDValue Lo = DAG.getNode(ShiftOpc, DL, ExtVT, RLo, ALo);
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SDValue Hi = DAG.getNode(ShiftOpc, DL, ExtVT, RHi, AHi);
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return getPack(DAG, Subtarget, DL, VT, Lo, Hi, !HiddenROTRAmt);
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return getPack(DAG, Subtarget, DL, VT, Lo, Hi, IsROTL);
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}
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assert((VT == MVT::v16i8 || VT == MVT::v32i8) && "Unsupported vXi8 type");
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@ -29982,15 +29988,15 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
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return DAG.getSelect(DL, SelVT, C, V0, V1);
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};
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// 'Hidden' ROTR is currently only profitable on AVX512 targets where we
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// have VPTERNLOG.
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unsigned ShiftLHS = ISD::SHL;
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unsigned ShiftRHS = ISD::SRL;
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if (HiddenROTRAmt && useVPTERNLOG(Subtarget, VT)) {
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std::swap(ShiftLHS, ShiftRHS);
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Amt = HiddenROTRAmt;
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// ISD::ROTR is currently only profitable on AVX512 targets with VPTERNLOG.
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if (!IsROTL && !useVPTERNLOG(Subtarget, VT)) {
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Amt = DAG.getNode(ISD::SUB, DL, VT, Z, Amt);
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IsROTL = true;
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}
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unsigned ShiftLHS = IsROTL ? ISD::SHL : ISD::SRL;
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unsigned ShiftRHS = IsROTL ? ISD::SRL : ISD::SHL;
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// Turn 'a' into a mask suitable for VSELECT: a = a << 5;
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// We can safely do this using i16 shifts as we're only interested in
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// the 3 lower bits of each byte.
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@ -30027,9 +30033,6 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
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return SignBitSelect(VT, Amt, M, R);
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}
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// ISD::ROT* uses modulo rotate amounts.
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Amt = DAG.getNode(ISD::AND, DL, VT, Amt, AmtMask);
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bool IsSplatAmt = DAG.isSplatValue(Amt);
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bool ConstantAmt = ISD::isBuildVectorOfConstantSDNodes(Amt.getNode());
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bool LegalVarShifts = supportedVectorVarShift(VT, Subtarget, ISD::SHL) &&
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@ -30038,13 +30041,25 @@ static SDValue LowerRotate(SDValue Op, const X86Subtarget &Subtarget,
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// Fallback for splats + all supported variable shifts.
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// Fallback for non-constants AVX2 vXi16 as well.
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if (IsSplatAmt || LegalVarShifts || (Subtarget.hasAVX2() && !ConstantAmt)) {
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Amt = DAG.getNode(ISD::AND, DL, VT, Amt, AmtMask);
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SDValue AmtR = DAG.getConstant(EltSizeInBits, DL, VT);
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AmtR = DAG.getNode(ISD::SUB, DL, VT, AmtR, Amt);
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SDValue SHL = DAG.getNode(ISD::SHL, DL, VT, R, Amt);
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SDValue SRL = DAG.getNode(ISD::SRL, DL, VT, R, AmtR);
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SDValue SHL = DAG.getNode(IsROTL ? ISD::SHL : ISD::SRL, DL, VT, R, Amt);
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SDValue SRL = DAG.getNode(IsROTL ? ISD::SRL : ISD::SHL, DL, VT, R, AmtR);
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return DAG.getNode(ISD::OR, DL, VT, SHL, SRL);
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}
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// Everything below assumes ISD::ROTL.
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if (!IsROTL) {
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Amt = DAG.getNode(ISD::SUB, DL, VT, Z, Amt);
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IsROTL = true;
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}
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// ISD::ROT* uses modulo rotate amounts.
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Amt = DAG.getNode(ISD::AND, DL, VT, Amt, AmtMask);
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assert(IsROTL && "Only ROTL supported");
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// As with shifts, attempt to convert the rotation amount to a multiplication
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// factor, fallback to general expansion.
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SDValue Scale = convertShiftLeftToScale(Amt, DL, Subtarget, DAG);
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@ -328,14 +328,12 @@ define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) nounwind {
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;
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; X64-AVX2-LABEL: rotr_v4i32:
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; X64-AVX2: # %bb.0:
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; X64-AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; X64-AVX2-NEXT: vpsubd %xmm1, %xmm2, %xmm1
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; X64-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [31,31,31,31]
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; X64-AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
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; X64-AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm2
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; X64-AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm2
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; X64-AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [32,32,32,32]
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; X64-AVX2-NEXT: vpsubd %xmm1, %xmm3, %xmm1
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; X64-AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
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; X64-AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
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; X64-AVX2-NEXT: vpor %xmm0, %xmm2, %xmm0
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; X64-AVX2-NEXT: retq
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%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %x, <4 x i32> %z)
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@ -232,14 +232,12 @@ define <4 x i32> @var_funnnel_v4i32(<4 x i32> %x, <4 x i32> %amt) nounwind {
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;
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; AVX2-LABEL: var_funnnel_v4i32:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX2-NEXT: vpsubd %xmm1, %xmm2, %xmm1
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [31,31,31,31]
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; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
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; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm2
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; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm2
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; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [32,32,32,32]
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; AVX2-NEXT: vpsubd %xmm1, %xmm3, %xmm1
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; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
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; AVX2-NEXT: vpor %xmm0, %xmm2, %xmm0
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; AVX2-NEXT: retq
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;
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@ -386,36 +384,32 @@ define <8 x i16> @var_funnnel_v8i16(<8 x i16> %x, <8 x i16> %amt) nounwind {
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;
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; AVX2-LABEL: var_funnnel_v8i16:
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; AVX2: # %bb.0:
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; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
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; AVX2-NEXT: vpsubw %xmm1, %xmm2, %xmm1
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; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
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; AVX2-NEXT: vmovdqa {{.*#+}} xmm2 = [16,16,16,16,16,16,16,16]
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; AVX2-NEXT: vpsubw %xmm1, %xmm2, %xmm2
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; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero
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; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
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; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
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; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
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; AVX2-NEXT: vpsrlvd %ymm2, %ymm0, %ymm2
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; AVX2-NEXT: vextracti128 $1, %ymm2, %xmm3
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||||
; AVX2-NEXT: vpackusdw %xmm3, %xmm2, %xmm2
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX2-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
|
||||
; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
|
||||
; AVX2-NEXT: vpshufb {{.*#+}} ymm0 = ymm0[0,1,4,5,8,9,12,13,u,u,u,u,u,u,u,u,16,17,20,21,24,25,28,29,u,u,u,u,u,u,u,u]
|
||||
; AVX2-NEXT: vpermq {{.*#+}} ymm0 = ymm0[0,2,2,3]
|
||||
; AVX2-NEXT: vpor %xmm2, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpor %xmm0, %xmm2, %xmm0
|
||||
; AVX2-NEXT: vzeroupper
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512F-LABEL: var_funnnel_v8i16:
|
||||
; AVX512F: # %bb.0:
|
||||
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512F-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
|
||||
; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
|
||||
; AVX512F-NEXT: vpsllvd %ymm2, %ymm0, %ymm2
|
||||
; AVX512F-NEXT: vpsrlvd %ymm2, %ymm0, %ymm2
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX512F-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
|
||||
; AVX512F-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
|
||||
; AVX512F-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
|
||||
; AVX512F-NEXT: vpor %ymm0, %ymm2, %ymm0
|
||||
; AVX512F-NEXT: vpmovdw %zmm0, %ymm0
|
||||
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $ymm0
|
||||
|
|
@ -424,16 +418,14 @@ define <8 x i16> @var_funnnel_v8i16(<8 x i16> %x, <8 x i16> %amt) nounwind {
|
|||
;
|
||||
; AVX512VL-LABEL: var_funnnel_v8i16:
|
||||
; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512VL-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
|
||||
; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} ymm2 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
|
||||
; AVX512VL-NEXT: vpsllvd %ymm2, %ymm0, %ymm2
|
||||
; AVX512VL-NEXT: vpsrlvd %ymm2, %ymm0, %ymm2
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX512VL-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
|
||||
; AVX512VL-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
|
||||
; AVX512VL-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
|
||||
; AVX512VL-NEXT: vpor %ymm0, %ymm2, %ymm0
|
||||
; AVX512VL-NEXT: vpmovdw %ymm0, %xmm0
|
||||
; AVX512VL-NEXT: vzeroupper
|
||||
|
|
@ -442,26 +434,22 @@ define <8 x i16> @var_funnnel_v8i16(<8 x i16> %x, <8 x i16> %amt) nounwind {
|
|||
; AVX512BW-LABEL: var_funnnel_v8i16:
|
||||
; AVX512BW: # %bb.0:
|
||||
; AVX512BW-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0
|
||||
; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512BW-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm2
|
||||
; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm2
|
||||
; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX512BW-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm0
|
||||
; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0
|
||||
; AVX512BW-NEXT: vpor %xmm0, %xmm2, %xmm0
|
||||
; AVX512BW-NEXT: vzeroupper
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512VLBW-LABEL: var_funnnel_v8i16:
|
||||
; AVX512VLBW: # %bb.0:
|
||||
; AVX512VLBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512VLBW-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX512VLBW-NEXT: vpsllvw %xmm1, %xmm0, %xmm2
|
||||
; AVX512VLBW-NEXT: vpsrlvw %xmm1, %xmm0, %xmm2
|
||||
; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX512VLBW-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX512VLBW-NEXT: vpsrlvw %xmm1, %xmm0, %xmm0
|
||||
; AVX512VLBW-NEXT: vpsllvw %xmm1, %xmm0, %xmm0
|
||||
; AVX512VLBW-NEXT: vpor %xmm0, %xmm2, %xmm0
|
||||
; AVX512VLBW-NEXT: retq
|
||||
;
|
||||
|
|
@ -975,103 +963,89 @@ define <4 x i32> @splatvar_funnnel_v4i32(<4 x i32> %x, <4 x i32> %amt) nounwind
|
|||
define <8 x i16> @splatvar_funnnel_v8i16(<8 x i16> %x, <8 x i16> %amt) nounwind {
|
||||
; SSE2-LABEL: splatvar_funnnel_v8i16:
|
||||
; SSE2: # %bb.0:
|
||||
; SSE2-NEXT: pxor %xmm2, %xmm2
|
||||
; SSE2-NEXT: psubw %xmm1, %xmm2
|
||||
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,0,0]
|
||||
; SSE2-NEXT: pand %xmm2, %xmm1
|
||||
; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,0,0,0]
|
||||
; SSE2-NEXT: pand %xmm1, %xmm2
|
||||
; SSE2-NEXT: movdqa %xmm0, %xmm3
|
||||
; SSE2-NEXT: psllw %xmm1, %xmm3
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16]
|
||||
; SSE2-NEXT: psubw %xmm2, %xmm1
|
||||
; SSE2-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
|
||||
; SSE2-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; SSE2-NEXT: psrlw %xmm1, %xmm0
|
||||
; SSE2-NEXT: psrlw %xmm2, %xmm3
|
||||
; SSE2-NEXT: movdqa {{.*#+}} xmm2 = [16,16,16,16,16,16,16,16]
|
||||
; SSE2-NEXT: psubw %xmm1, %xmm2
|
||||
; SSE2-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1]
|
||||
; SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; SSE2-NEXT: psllw %xmm2, %xmm0
|
||||
; SSE2-NEXT: por %xmm3, %xmm0
|
||||
; SSE2-NEXT: retq
|
||||
;
|
||||
; SSE41-LABEL: splatvar_funnnel_v8i16:
|
||||
; SSE41: # %bb.0:
|
||||
; SSE41-NEXT: pxor %xmm2, %xmm2
|
||||
; SSE41-NEXT: psubw %xmm1, %xmm2
|
||||
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2
|
||||
; SSE41-NEXT: pmovzxwq {{.*#+}} xmm1 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
|
||||
; SSE41-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1
|
||||
; SSE41-NEXT: pmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; SSE41-NEXT: movdqa %xmm0, %xmm3
|
||||
; SSE41-NEXT: psllw %xmm1, %xmm3
|
||||
; SSE41-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16]
|
||||
; SSE41-NEXT: psubw %xmm2, %xmm1
|
||||
; SSE41-NEXT: pmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; SSE41-NEXT: psrlw %xmm1, %xmm0
|
||||
; SSE41-NEXT: psrlw %xmm2, %xmm3
|
||||
; SSE41-NEXT: movdqa {{.*#+}} xmm2 = [16,16,16,16,16,16,16,16]
|
||||
; SSE41-NEXT: psubw %xmm1, %xmm2
|
||||
; SSE41-NEXT: pmovzxwq {{.*#+}} xmm1 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero
|
||||
; SSE41-NEXT: psllw %xmm1, %xmm0
|
||||
; SSE41-NEXT: por %xmm3, %xmm0
|
||||
; SSE41-NEXT: retq
|
||||
;
|
||||
; AVX-LABEL: splatvar_funnnel_v8i16:
|
||||
; AVX: # %bb.0:
|
||||
; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX-NEXT: vpsllw %xmm2, %xmm0, %xmm2
|
||||
; AVX-NEXT: vpsrlw %xmm2, %xmm0, %xmm2
|
||||
; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpsllw %xmm1, %xmm0, %xmm0
|
||||
; AVX-NEXT: vpor %xmm0, %xmm2, %xmm0
|
||||
; AVX-NEXT: retq
|
||||
;
|
||||
; AVX512F-LABEL: splatvar_funnnel_v8i16:
|
||||
; AVX512F: # %bb.0:
|
||||
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512F-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX512F-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512F-NEXT: vpsllw %xmm2, %xmm0, %xmm2
|
||||
; AVX512F-NEXT: vpsrlw %xmm2, %xmm0, %xmm2
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX512F-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX512F-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512F-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
|
||||
; AVX512F-NEXT: vpsllw %xmm1, %xmm0, %xmm0
|
||||
; AVX512F-NEXT: vpor %xmm0, %xmm2, %xmm0
|
||||
; AVX512F-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: splatvar_funnnel_v8i16:
|
||||
; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512VL-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512VL-NEXT: vpsllw %xmm2, %xmm0, %xmm2
|
||||
; AVX512VL-NEXT: vpsrlw %xmm2, %xmm0, %xmm2
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX512VL-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512VL-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: vpsllw %xmm1, %xmm0, %xmm0
|
||||
; AVX512VL-NEXT: vpor %xmm0, %xmm2, %xmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
;
|
||||
; AVX512BW-LABEL: splatvar_funnnel_v8i16:
|
||||
; AVX512BW: # %bb.0:
|
||||
; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512BW-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX512BW-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512BW-NEXT: vpsllw %xmm2, %xmm0, %xmm2
|
||||
; AVX512BW-NEXT: vpsrlw %xmm2, %xmm0, %xmm2
|
||||
; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX512BW-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX512BW-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512BW-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
|
||||
; AVX512BW-NEXT: vpsllw %xmm1, %xmm0, %xmm0
|
||||
; AVX512BW-NEXT: vpor %xmm0, %xmm2, %xmm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512VLBW-LABEL: splatvar_funnnel_v8i16:
|
||||
; AVX512VLBW: # %bb.0:
|
||||
; AVX512VLBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512VLBW-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX512VLBW-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512VLBW-NEXT: vpsllw %xmm2, %xmm0, %xmm2
|
||||
; AVX512VLBW-NEXT: vpsrlw %xmm2, %xmm0, %xmm2
|
||||
; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX512VLBW-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX512VLBW-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512VLBW-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
|
||||
; AVX512VLBW-NEXT: vpsllw %xmm1, %xmm0, %xmm0
|
||||
; AVX512VLBW-NEXT: vpor %xmm0, %xmm2, %xmm0
|
||||
; AVX512VLBW-NEXT: retq
|
||||
;
|
||||
|
|
@ -1109,18 +1083,16 @@ define <8 x i16> @splatvar_funnnel_v8i16(<8 x i16> %x, <8 x i16> %amt) nounwind
|
|||
;
|
||||
; X86-SSE2-LABEL: splatvar_funnnel_v8i16:
|
||||
; X86-SSE2: # %bb.0:
|
||||
; X86-SSE2-NEXT: pxor %xmm2, %xmm2
|
||||
; X86-SSE2-NEXT: psubw %xmm1, %xmm2
|
||||
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm2
|
||||
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,0,0]
|
||||
; X86-SSE2-NEXT: pand %xmm2, %xmm1
|
||||
; X86-SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}, %xmm1
|
||||
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [65535,0,0,0]
|
||||
; X86-SSE2-NEXT: pand %xmm1, %xmm2
|
||||
; X86-SSE2-NEXT: movdqa %xmm0, %xmm3
|
||||
; X86-SSE2-NEXT: psllw %xmm1, %xmm3
|
||||
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16]
|
||||
; X86-SSE2-NEXT: psubw %xmm2, %xmm1
|
||||
; X86-SSE2-NEXT: pslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm1[0,1]
|
||||
; X86-SSE2-NEXT: psrldq {{.*#+}} xmm1 = xmm1[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; X86-SSE2-NEXT: psrlw %xmm1, %xmm0
|
||||
; X86-SSE2-NEXT: psrlw %xmm2, %xmm3
|
||||
; X86-SSE2-NEXT: movdqa {{.*#+}} xmm2 = [16,16,16,16,16,16,16,16]
|
||||
; X86-SSE2-NEXT: psubw %xmm1, %xmm2
|
||||
; X86-SSE2-NEXT: pslldq {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm2[0,1]
|
||||
; X86-SSE2-NEXT: psrldq {{.*#+}} xmm2 = xmm2[14,15],zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero
|
||||
; X86-SSE2-NEXT: psllw %xmm2, %xmm0
|
||||
; X86-SSE2-NEXT: por %xmm3, %xmm0
|
||||
; X86-SSE2-NEXT: retl
|
||||
%splat = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> zeroinitializer
|
||||
|
|
|
|||
|
|
@ -171,14 +171,12 @@ define <8 x i32> @var_funnnel_v8i32(<8 x i32> %x, <8 x i32> %amt) nounwind {
|
|||
;
|
||||
; AVX2-LABEL: var_funnnel_v8i32:
|
||||
; AVX2: # %bb.0:
|
||||
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX2-NEXT: vpsubd %ymm1, %ymm2, %ymm1
|
||||
; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm2 = [31,31,31,31,31,31,31,31]
|
||||
; AVX2-NEXT: vpand %ymm2, %ymm1, %ymm1
|
||||
; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm2
|
||||
; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm2
|
||||
; AVX2-NEXT: vpbroadcastd {{.*#+}} ymm3 = [32,32,32,32,32,32,32,32]
|
||||
; AVX2-NEXT: vpsubd %ymm1, %ymm3, %ymm1
|
||||
; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
|
||||
; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
|
||||
; AVX2-NEXT: vpor %ymm0, %ymm2, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
|
|
@ -290,23 +288,22 @@ define <16 x i16> @var_funnnel_v16i16(<16 x i16> %x, <16 x i16> %amt) nounwind {
|
|||
; AVX2: # %bb.0:
|
||||
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm3 = ymm2[4],ymm0[4],ymm2[5],ymm0[5],ymm2[6],ymm0[6],ymm2[7],ymm0[7],ymm2[12],ymm0[12],ymm2[13],ymm0[13],ymm2[14],ymm0[14],ymm2[15],ymm0[15]
|
||||
; AVX2-NEXT: vpsubw %ymm1, %ymm2, %ymm1
|
||||
; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
|
||||
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm4 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
|
||||
; AVX2-NEXT: vpsllvd %ymm4, %ymm3, %ymm4
|
||||
; AVX2-NEXT: vpsrlvd %ymm4, %ymm3, %ymm4
|
||||
; AVX2-NEXT: vpsrld $16, %ymm4, %ymm4
|
||||
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm0 = ymm2[0],ymm0[0],ymm2[1],ymm0[1],ymm2[2],ymm0[2],ymm2[3],ymm0[3],ymm2[8],ymm0[8],ymm2[9],ymm0[9],ymm2[10],ymm0[10],ymm2[11],ymm0[11]
|
||||
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm5 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
|
||||
; AVX2-NEXT: vpsllvd %ymm5, %ymm0, %ymm5
|
||||
; AVX2-NEXT: vpsrlvd %ymm5, %ymm0, %ymm5
|
||||
; AVX2-NEXT: vpsrld $16, %ymm5, %ymm5
|
||||
; AVX2-NEXT: vpackusdw %ymm4, %ymm5, %ymm4
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} ymm5 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
|
||||
; AVX2-NEXT: vpsubw %ymm1, %ymm5, %ymm1
|
||||
; AVX2-NEXT: vpunpckhwd {{.*#+}} ymm5 = ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15]
|
||||
; AVX2-NEXT: vpsrlvd %ymm5, %ymm3, %ymm3
|
||||
; AVX2-NEXT: vpsllvd %ymm5, %ymm3, %ymm3
|
||||
; AVX2-NEXT: vpsrld $16, %ymm3, %ymm3
|
||||
; AVX2-NEXT: vpunpcklwd {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11]
|
||||
; AVX2-NEXT: vpsrlvd %ymm1, %ymm0, %ymm0
|
||||
; AVX2-NEXT: vpsllvd %ymm1, %ymm0, %ymm0
|
||||
; AVX2-NEXT: vpsrld $16, %ymm0, %ymm0
|
||||
; AVX2-NEXT: vpackusdw %ymm3, %ymm0, %ymm0
|
||||
; AVX2-NEXT: vpor %ymm0, %ymm4, %ymm0
|
||||
|
|
@ -314,32 +311,28 @@ define <16 x i16> @var_funnnel_v16i16(<16 x i16> %x, <16 x i16> %amt) nounwind {
|
|||
;
|
||||
; AVX512F-LABEL: var_funnnel_v16i16:
|
||||
; AVX512F: # %bb.0:
|
||||
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512F-NEXT: vpsubw %ymm1, %ymm2, %ymm1
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
|
||||
; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
|
||||
; AVX512F-NEXT: vpsllvd %zmm2, %zmm0, %zmm2
|
||||
; AVX512F-NEXT: vpsrlvd %zmm2, %zmm0, %zmm2
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm3 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
|
||||
; AVX512F-NEXT: vpsubw %ymm1, %ymm3, %ymm1
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
|
||||
; AVX512F-NEXT: vpsrlvd %zmm1, %zmm0, %zmm0
|
||||
; AVX512F-NEXT: vpsllvd %zmm1, %zmm0, %zmm0
|
||||
; AVX512F-NEXT: vpord %zmm0, %zmm2, %zmm0
|
||||
; AVX512F-NEXT: vpmovdw %zmm0, %ymm0
|
||||
; AVX512F-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: var_funnnel_v16i16:
|
||||
; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512VL-NEXT: vpsubw %ymm1, %ymm2, %ymm1
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
|
||||
; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
|
||||
; AVX512VL-NEXT: vpsllvd %zmm2, %zmm0, %zmm2
|
||||
; AVX512VL-NEXT: vpsrlvd %zmm2, %zmm0, %zmm2
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm3 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
|
||||
; AVX512VL-NEXT: vpsubw %ymm1, %ymm3, %ymm1
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
|
||||
; AVX512VL-NEXT: vpsrlvd %zmm1, %zmm0, %zmm0
|
||||
; AVX512VL-NEXT: vpsllvd %zmm1, %zmm0, %zmm0
|
||||
; AVX512VL-NEXT: vpord %zmm0, %zmm2, %zmm0
|
||||
; AVX512VL-NEXT: vpmovdw %zmm0, %ymm0
|
||||
; AVX512VL-NEXT: retq
|
||||
|
|
@ -347,25 +340,21 @@ define <16 x i16> @var_funnnel_v16i16(<16 x i16> %x, <16 x i16> %amt) nounwind {
|
|||
; AVX512BW-LABEL: var_funnnel_v16i16:
|
||||
; AVX512BW: # %bb.0:
|
||||
; AVX512BW-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0
|
||||
; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512BW-NEXT: vpsubw %ymm1, %ymm2, %ymm1
|
||||
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
|
||||
; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm2
|
||||
; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm2
|
||||
; AVX512BW-NEXT: vmovdqa {{.*#+}} ymm3 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
|
||||
; AVX512BW-NEXT: vpsubw %ymm1, %ymm3, %ymm1
|
||||
; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm0
|
||||
; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm0
|
||||
; AVX512BW-NEXT: vpor %ymm0, %ymm2, %ymm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512VLBW-LABEL: var_funnnel_v16i16:
|
||||
; AVX512VLBW: # %bb.0:
|
||||
; AVX512VLBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512VLBW-NEXT: vpsubw %ymm1, %ymm2, %ymm1
|
||||
; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
|
||||
; AVX512VLBW-NEXT: vpsllvw %ymm1, %ymm0, %ymm2
|
||||
; AVX512VLBW-NEXT: vpsrlvw %ymm1, %ymm0, %ymm2
|
||||
; AVX512VLBW-NEXT: vmovdqa {{.*#+}} ymm3 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
|
||||
; AVX512VLBW-NEXT: vpsubw %ymm1, %ymm3, %ymm1
|
||||
; AVX512VLBW-NEXT: vpsrlvw %ymm1, %ymm0, %ymm0
|
||||
; AVX512VLBW-NEXT: vpsllvw %ymm1, %ymm0, %ymm0
|
||||
; AVX512VLBW-NEXT: vpor %ymm0, %ymm2, %ymm0
|
||||
; AVX512VLBW-NEXT: retq
|
||||
;
|
||||
|
|
@ -801,90 +790,78 @@ define <8 x i32> @splatvar_funnnel_v8i32(<8 x i32> %x, <8 x i32> %amt) nounwind
|
|||
define <16 x i16> @splatvar_funnnel_v16i16(<16 x i16> %x, <16 x i16> %amt) nounwind {
|
||||
; AVX1-LABEL: splatvar_funnnel_v16i16:
|
||||
; AVX1: # %bb.0:
|
||||
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
|
||||
; AVX1-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
|
||||
; AVX1-NEXT: vpsllw %xmm2, %xmm3, %xmm4
|
||||
; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm3 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX1-NEXT: vpsrlw %xmm3, %xmm2, %xmm4
|
||||
; AVX1-NEXT: vmovdqa {{.*#+}} xmm5 = [16,16,16,16,16,16,16,16]
|
||||
; AVX1-NEXT: vpsubw %xmm1, %xmm5, %xmm1
|
||||
; AVX1-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX1-NEXT: vpsrlw %xmm1, %xmm3, %xmm3
|
||||
; AVX1-NEXT: vpor %xmm3, %xmm4, %xmm3
|
||||
; AVX1-NEXT: vpsllw %xmm2, %xmm0, %xmm2
|
||||
; AVX1-NEXT: vpsrlw %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpor %xmm0, %xmm2, %xmm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm3, %ymm0, %ymm0
|
||||
; AVX1-NEXT: vpsllw %xmm1, %xmm2, %xmm2
|
||||
; AVX1-NEXT: vpor %xmm2, %xmm4, %xmm2
|
||||
; AVX1-NEXT: vpsrlw %xmm3, %xmm0, %xmm3
|
||||
; AVX1-NEXT: vpsllw %xmm1, %xmm0, %xmm0
|
||||
; AVX1-NEXT: vpor %xmm0, %xmm3, %xmm0
|
||||
; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0
|
||||
; AVX1-NEXT: retq
|
||||
;
|
||||
; AVX2-LABEL: splatvar_funnnel_v16i16:
|
||||
; AVX2: # %bb.0:
|
||||
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX2-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX2-NEXT: vpsllw %xmm2, %ymm0, %ymm2
|
||||
; AVX2-NEXT: vpsrlw %xmm2, %ymm0, %ymm2
|
||||
; AVX2-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX2-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX2-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX2-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
|
||||
; AVX2-NEXT: vpsllw %xmm1, %ymm0, %ymm0
|
||||
; AVX2-NEXT: vpor %ymm0, %ymm2, %ymm0
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
; AVX512F-LABEL: splatvar_funnnel_v16i16:
|
||||
; AVX512F: # %bb.0:
|
||||
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512F-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX512F-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512F-NEXT: vpsllw %xmm2, %ymm0, %ymm2
|
||||
; AVX512F-NEXT: vpsrlw %xmm2, %ymm0, %ymm2
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX512F-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX512F-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512F-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
|
||||
; AVX512F-NEXT: vpsllw %xmm1, %ymm0, %ymm0
|
||||
; AVX512F-NEXT: vpor %ymm0, %ymm2, %ymm0
|
||||
; AVX512F-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: splatvar_funnnel_v16i16:
|
||||
; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512VL-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512VL-NEXT: vpsllw %xmm2, %ymm0, %ymm2
|
||||
; AVX512VL-NEXT: vpsrlw %xmm2, %ymm0, %ymm2
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX512VL-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512VL-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
|
||||
; AVX512VL-NEXT: vpsllw %xmm1, %ymm0, %ymm0
|
||||
; AVX512VL-NEXT: vpor %ymm0, %ymm2, %ymm0
|
||||
; AVX512VL-NEXT: retq
|
||||
;
|
||||
; AVX512BW-LABEL: splatvar_funnnel_v16i16:
|
||||
; AVX512BW: # %bb.0:
|
||||
; AVX512BW-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512BW-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX512BW-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512BW-NEXT: vpsllw %xmm2, %ymm0, %ymm2
|
||||
; AVX512BW-NEXT: vpsrlw %xmm2, %ymm0, %ymm2
|
||||
; AVX512BW-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX512BW-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX512BW-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512BW-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
|
||||
; AVX512BW-NEXT: vpsllw %xmm1, %ymm0, %ymm0
|
||||
; AVX512BW-NEXT: vpor %ymm0, %ymm2, %ymm0
|
||||
; AVX512BW-NEXT: retq
|
||||
;
|
||||
; AVX512VLBW-LABEL: splatvar_funnnel_v16i16:
|
||||
; AVX512VLBW: # %bb.0:
|
||||
; AVX512VLBW-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512VLBW-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX512VLBW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX512VLBW-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512VLBW-NEXT: vpsllw %xmm2, %ymm0, %ymm2
|
||||
; AVX512VLBW-NEXT: vpsrlw %xmm2, %ymm0, %ymm2
|
||||
; AVX512VLBW-NEXT: vmovdqa {{.*#+}} xmm3 = [16,16,16,16,16,16,16,16]
|
||||
; AVX512VLBW-NEXT: vpsubw %xmm1, %xmm3, %xmm1
|
||||
; AVX512VLBW-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512VLBW-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
|
||||
; AVX512VLBW-NEXT: vpsllw %xmm1, %ymm0, %ymm0
|
||||
; AVX512VLBW-NEXT: vpor %ymm0, %ymm2, %ymm0
|
||||
; AVX512VLBW-NEXT: retq
|
||||
;
|
||||
|
|
|
|||
|
|
@ -36,29 +36,26 @@ define <16 x i32> @var_funnnel_v16i32(<16 x i32> %x, <16 x i32> %amt) nounwind {
|
|||
define <32 x i16> @var_funnnel_v32i16(<32 x i16> %x, <32 x i16> %amt) nounwind {
|
||||
; AVX512F-LABEL: var_funnnel_v32i16:
|
||||
; AVX512F: # %bb.0:
|
||||
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512F-NEXT: vpsubw %ymm1, %ymm2, %ymm3
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; AVX512F-NEXT: vpand %ymm4, %ymm3, %ymm3
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm5 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm6 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
|
||||
; AVX512F-NEXT: vpsllvd %zmm5, %zmm6, %zmm5
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm7 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
|
||||
; AVX512F-NEXT: vpsubw %ymm3, %ymm7, %ymm3
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm3
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm4 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm5 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
|
||||
; AVX512F-NEXT: vpsrlvd %zmm4, %zmm5, %zmm4
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} ymm6 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
|
||||
; AVX512F-NEXT: vpsubw %ymm3, %ymm6, %ymm3
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm3 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero
|
||||
; AVX512F-NEXT: vpsrlvd %zmm3, %zmm6, %zmm3
|
||||
; AVX512F-NEXT: vpord %zmm3, %zmm5, %zmm3
|
||||
; AVX512F-NEXT: vpsllvd %zmm3, %zmm5, %zmm3
|
||||
; AVX512F-NEXT: vpord %zmm3, %zmm4, %zmm3
|
||||
; AVX512F-NEXT: vpmovdw %zmm3, %ymm3
|
||||
; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm1
|
||||
; AVX512F-NEXT: vpsubw %ymm1, %ymm2, %ymm1
|
||||
; AVX512F-NEXT: vpand %ymm4, %ymm1, %ymm1
|
||||
; AVX512F-NEXT: vpand %ymm2, %ymm1, %ymm1
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
|
||||
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm0
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
|
||||
; AVX512F-NEXT: vpsllvd %zmm2, %zmm0, %zmm2
|
||||
; AVX512F-NEXT: vpsubw %ymm1, %ymm7, %ymm1
|
||||
; AVX512F-NEXT: vpsrlvd %zmm2, %zmm0, %zmm2
|
||||
; AVX512F-NEXT: vpsubw %ymm1, %ymm6, %ymm1
|
||||
; AVX512F-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
|
||||
; AVX512F-NEXT: vpsrlvd %zmm1, %zmm0, %zmm0
|
||||
; AVX512F-NEXT: vpsllvd %zmm1, %zmm0, %zmm0
|
||||
; AVX512F-NEXT: vpord %zmm0, %zmm2, %zmm0
|
||||
; AVX512F-NEXT: vpmovdw %zmm0, %ymm0
|
||||
; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm0
|
||||
|
|
@ -66,29 +63,26 @@ define <32 x i16> @var_funnnel_v32i16(<32 x i16> %x, <32 x i16> %amt) nounwind {
|
|||
;
|
||||
; AVX512VL-LABEL: var_funnnel_v32i16:
|
||||
; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512VL-NEXT: vpsubw %ymm1, %ymm2, %ymm3
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; AVX512VL-NEXT: vpand %ymm4, %ymm3, %ymm3
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} zmm5 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} zmm6 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
|
||||
; AVX512VL-NEXT: vpsllvd %zmm5, %zmm6, %zmm5
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm7 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
|
||||
; AVX512VL-NEXT: vpsubw %ymm3, %ymm7, %ymm3
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
|
||||
; AVX512VL-NEXT: vpand %ymm2, %ymm1, %ymm3
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} zmm4 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} zmm5 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
|
||||
; AVX512VL-NEXT: vpsrlvd %zmm4, %zmm5, %zmm4
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm6 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
|
||||
; AVX512VL-NEXT: vpsubw %ymm3, %ymm6, %ymm3
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} zmm3 = ymm3[0],zero,ymm3[1],zero,ymm3[2],zero,ymm3[3],zero,ymm3[4],zero,ymm3[5],zero,ymm3[6],zero,ymm3[7],zero,ymm3[8],zero,ymm3[9],zero,ymm3[10],zero,ymm3[11],zero,ymm3[12],zero,ymm3[13],zero,ymm3[14],zero,ymm3[15],zero
|
||||
; AVX512VL-NEXT: vpsrlvd %zmm3, %zmm6, %zmm3
|
||||
; AVX512VL-NEXT: vpord %zmm3, %zmm5, %zmm3
|
||||
; AVX512VL-NEXT: vpsllvd %zmm3, %zmm5, %zmm3
|
||||
; AVX512VL-NEXT: vpord %zmm3, %zmm4, %zmm3
|
||||
; AVX512VL-NEXT: vpmovdw %zmm3, %ymm3
|
||||
; AVX512VL-NEXT: vextracti64x4 $1, %zmm1, %ymm1
|
||||
; AVX512VL-NEXT: vpsubw %ymm1, %ymm2, %ymm1
|
||||
; AVX512VL-NEXT: vpand %ymm4, %ymm1, %ymm1
|
||||
; AVX512VL-NEXT: vpand %ymm2, %ymm1, %ymm1
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
|
||||
; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm0
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero
|
||||
; AVX512VL-NEXT: vpsllvd %zmm2, %zmm0, %zmm2
|
||||
; AVX512VL-NEXT: vpsubw %ymm1, %ymm7, %ymm1
|
||||
; AVX512VL-NEXT: vpsrlvd %zmm2, %zmm0, %zmm2
|
||||
; AVX512VL-NEXT: vpsubw %ymm1, %ymm6, %ymm1
|
||||
; AVX512VL-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero
|
||||
; AVX512VL-NEXT: vpsrlvd %zmm1, %zmm0, %zmm0
|
||||
; AVX512VL-NEXT: vpsllvd %zmm1, %zmm0, %zmm0
|
||||
; AVX512VL-NEXT: vpord %zmm0, %zmm2, %zmm0
|
||||
; AVX512VL-NEXT: vpmovdw %zmm0, %ymm0
|
||||
; AVX512VL-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm0
|
||||
|
|
@ -308,40 +302,36 @@ define <16 x i32> @splatvar_funnnel_v16i32(<16 x i32> %x, <16 x i32> %amt) nounw
|
|||
define <32 x i16> @splatvar_funnnel_v32i16(<32 x i16> %x, <32 x i16> %amt) nounwind {
|
||||
; AVX512F-LABEL: splatvar_funnnel_v32i16:
|
||||
; AVX512F: # %bb.0:
|
||||
; AVX512F-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512F-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm2
|
||||
; AVX512F-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX512F-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3
|
||||
; AVX512F-NEXT: vpsllw %xmm2, %ymm3, %ymm4
|
||||
; AVX512F-NEXT: vpsllw %xmm2, %ymm0, %ymm2
|
||||
; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm2
|
||||
; AVX512F-NEXT: vpmovzxwq {{.*#+}} xmm3 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512F-NEXT: vpsrlw %xmm3, %ymm2, %ymm4
|
||||
; AVX512F-NEXT: vpsrlw %xmm3, %ymm0, %ymm3
|
||||
; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm3, %zmm3
|
||||
; AVX512F-NEXT: vmovdqa {{.*#+}} xmm4 = [16,16,16,16,16,16,16,16]
|
||||
; AVX512F-NEXT: vpsubw %xmm1, %xmm4, %xmm1
|
||||
; AVX512F-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512F-NEXT: vpsrlw %xmm1, %ymm3, %ymm3
|
||||
; AVX512F-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
|
||||
; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0
|
||||
; AVX512F-NEXT: vporq %zmm0, %zmm2, %zmm0
|
||||
; AVX512F-NEXT: vpsllw %xmm1, %ymm2, %ymm2
|
||||
; AVX512F-NEXT: vpsllw %xmm1, %ymm0, %ymm0
|
||||
; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
|
||||
; AVX512F-NEXT: vporq %zmm0, %zmm3, %zmm0
|
||||
; AVX512F-NEXT: retq
|
||||
;
|
||||
; AVX512VL-LABEL: splatvar_funnnel_v32i16:
|
||||
; AVX512VL: # %bb.0:
|
||||
; AVX512VL-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX512VL-NEXT: vpsubw %xmm1, %xmm2, %xmm1
|
||||
; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm2
|
||||
; AVX512VL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
|
||||
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512VL-NEXT: vextracti64x4 $1, %zmm0, %ymm3
|
||||
; AVX512VL-NEXT: vpsllw %xmm2, %ymm3, %ymm4
|
||||
; AVX512VL-NEXT: vpsllw %xmm2, %ymm0, %ymm2
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||||
; AVX512VL-NEXT: vinserti64x4 $1, %ymm4, %zmm2, %zmm2
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||||
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm3 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
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||||
; AVX512VL-NEXT: vpsrlw %xmm3, %ymm2, %ymm4
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||||
; AVX512VL-NEXT: vpsrlw %xmm3, %ymm0, %ymm3
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||||
; AVX512VL-NEXT: vinserti64x4 $1, %ymm4, %zmm3, %zmm3
|
||||
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm4 = [16,16,16,16,16,16,16,16]
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||||
; AVX512VL-NEXT: vpsubw %xmm1, %xmm4, %xmm1
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||||
; AVX512VL-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero
|
||||
; AVX512VL-NEXT: vpsrlw %xmm1, %ymm3, %ymm3
|
||||
; AVX512VL-NEXT: vpsrlw %xmm1, %ymm0, %ymm0
|
||||
; AVX512VL-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0
|
||||
; AVX512VL-NEXT: vporq %zmm0, %zmm2, %zmm0
|
||||
; AVX512VL-NEXT: vpsllw %xmm1, %ymm2, %ymm2
|
||||
; AVX512VL-NEXT: vpsllw %xmm1, %ymm0, %ymm0
|
||||
; AVX512VL-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0
|
||||
; AVX512VL-NEXT: vporq %zmm0, %zmm3, %zmm0
|
||||
; AVX512VL-NEXT: retq
|
||||
;
|
||||
; AVX512BW-LABEL: splatvar_funnnel_v32i16:
|
||||
|
|
|
|||
|
|
@ -83,14 +83,12 @@ define <2 x i32> @var_funnnel_v2i32(<2 x i32> %x, <2 x i32> %amt) nounwind {
|
|||
;
|
||||
; AVX2-LABEL: var_funnnel_v2i32:
|
||||
; AVX2: # %bb.0:
|
||||
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
|
||||
; AVX2-NEXT: vpsubd %xmm1, %xmm2, %xmm1
|
||||
; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [31,31,31,31]
|
||||
; AVX2-NEXT: vpand %xmm2, %xmm1, %xmm1
|
||||
; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm2
|
||||
; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm2
|
||||
; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm3 = [32,32,32,32]
|
||||
; AVX2-NEXT: vpsubd %xmm1, %xmm3, %xmm1
|
||||
; AVX2-NEXT: vpsrlvd %xmm1, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpsllvd %xmm1, %xmm0, %xmm0
|
||||
; AVX2-NEXT: vpor %xmm0, %xmm2, %xmm0
|
||||
; AVX2-NEXT: retq
|
||||
;
|
||||
|
|
|
|||
Loading…
Reference in New Issue