forked from OSchip/llvm-project
increase the accuracy of register pressure computation in the presence of dead definitions by using live intervals, if available, to identify dead definitions and proceed accordingly.
llvm-svn: 194286
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2fca51d3b4
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@ -1096,6 +1096,14 @@ void MachineVerifier::checkLiveness(const MachineOperand *MO, unsigned MONum) {
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report("No live segment at def", MO, MONum);
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report("No live segment at def", MO, MONum);
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*OS << DefIdx << " is not live in " << LI << '\n';
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*OS << DefIdx << " is not live in " << LI << '\n';
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}
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}
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// Check that, if the dead def flag is present, LiveInts agree.
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if (MO->isDead()) {
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LiveQueryResult LRQ = LI.Query(DefIdx);
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if (!LRQ.isDeadDef()) {
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report("Live range continues after dead def flag", MO, MONum);
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*OS << "Live range: " << LI << '\n';
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}
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}
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} else {
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} else {
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report("Virtual register has no Live interval", MO, MONum);
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report("Virtual register has no Live interval", MO, MONum);
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}
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}
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@ -1517,22 +1525,13 @@ void MachineVerifier::verifyLiveRangeSegment(const LiveRange &LR,
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// A live segment can end with either a redefinition, a kill flag on a
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// A live segment can end with either a redefinition, a kill flag on a
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// use, or a dead flag on a def.
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// use, or a dead flag on a def.
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bool hasRead = false;
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bool hasRead = false;
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bool hasDeadDef = false;
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for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
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for (ConstMIBundleOperands MOI(MI); MOI.isValid(); ++MOI) {
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if (!MOI->isReg() || MOI->getReg() != Reg)
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if (!MOI->isReg() || MOI->getReg() != Reg)
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continue;
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continue;
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if (MOI->readsReg())
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if (MOI->readsReg())
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hasRead = true;
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hasRead = true;
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if (MOI->isDef() && MOI->isDead())
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hasDeadDef = true;
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}
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}
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if (!S.end.isDead()) {
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if (S.end.isDead()) {
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if (!hasDeadDef) {
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report("Instruction doesn't have a dead def operand", MI);
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*OS << S << " in " << LR << '\n';
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}
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} else {
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if (!hasRead) {
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if (!hasRead) {
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report("Instruction ending live segment doesn't read the register", MI);
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report("Instruction ending live segment doesn't read the register", MI);
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*OS << S << " in " << LR << '\n';
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*OS << S << " in " << LR << '\n';
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@ -498,10 +498,20 @@ bool RegPressureTracker::recede(SmallVectorImpl<unsigned> *LiveUses,
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// TODO: consider earlyclobbers?
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// TODO: consider earlyclobbers?
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for (unsigned i = 0, e = RegOpers.Defs.size(); i < e; ++i) {
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for (unsigned i = 0, e = RegOpers.Defs.size(); i < e; ++i) {
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unsigned Reg = RegOpers.Defs[i];
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unsigned Reg = RegOpers.Defs[i];
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if (LiveRegs.erase(Reg))
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bool DeadDef = false;
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decreaseRegPressure(Reg);
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if (RequireIntervals) {
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else
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const LiveRange *LR = getLiveRange(Reg);
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discoverLiveOut(Reg);
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if (LR) {
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LiveQueryResult LRQ = LR->Query(SlotIdx);
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DeadDef = LRQ.isDeadDef();
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}
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}
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if (!DeadDef) {
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if (LiveRegs.erase(Reg))
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decreaseRegPressure(Reg);
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else
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discoverLiveOut(Reg);
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}
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}
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}
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// Generate liveness for uses.
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// Generate liveness for uses.
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@ -702,8 +712,19 @@ void RegPressureTracker::bumpUpwardPressure(const MachineInstr *MI) {
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// Kill liveness at live defs.
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// Kill liveness at live defs.
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for (unsigned i = 0, e = RegOpers.Defs.size(); i < e; ++i) {
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for (unsigned i = 0, e = RegOpers.Defs.size(); i < e; ++i) {
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unsigned Reg = RegOpers.Defs[i];
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unsigned Reg = RegOpers.Defs[i];
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if (!containsReg(RegOpers.Uses, Reg))
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bool DeadDef = false;
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decreaseRegPressure(Reg);
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if (RequireIntervals) {
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const LiveRange *LR = getLiveRange(Reg);
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if (LR) {
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SlotIndex SlotIdx = LIS->getInstructionIndex(MI);
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LiveQueryResult LRQ = LR->Query(SlotIdx);
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DeadDef = LRQ.isDeadDef();
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}
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}
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if (!DeadDef) {
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if (!containsReg(RegOpers.Uses, Reg))
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decreaseRegPressure(Reg);
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}
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}
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}
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// Generate liveness for uses.
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// Generate liveness for uses.
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for (unsigned i = 0, e = RegOpers.Uses.size(); i < e; ++i) {
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for (unsigned i = 0, e = RegOpers.Uses.size(); i < e; ++i) {
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