maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[AArch64][GlobalISel]Legalise some vector types for min/max 

Differential Revision: https://reviews.llvm.org/D105200
This commit is contained in:
Irina Dobrescu 2021-06-30 15:49:48 +01:00
parent 3eb2158f4f
commit 71d5b0a757
2 changed files with 131 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
View File

@ -168,6 +168,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder({G_SMULH, G_UMULH}).legalFor({s32, s64});
getActionDefinitionsBuilder({G_SMIN, G_SMAX, G_UMIN, G_UMAX})
.legalFor({v8s8, v16s8, v4s16, v8s16, v2s32, v4s32})
.lowerIf([=](const LegalityQuery &Q) { return Q.Types[0].isScalar(); });
getActionDefinitionsBuilder(

130
llvm/test/CodeGen/AArch64/GlobalISel/legalize-min-max.mir Normal file
View File

@ -0,0 +1,130 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-- -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
---
name: v8s8_smin
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: v8s8_smin
; CHECK: liveins: $x0
; CHECK: %vec:_(<8 x s8>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF
; CHECK: %smin:_(<8 x s8>) = G_SMIN %vec, %vec1
; CHECK: $x0 = COPY %smin(<8 x s8>)
; CHECK: RET_ReallyLR implicit $x0
%vec:_(<8 x s8>) = G_IMPLICIT_DEF
%vec1:_(<8 x s8>) = G_IMPLICIT_DEF
%smin:_(<8 x s8>) = G_SMIN %vec, %vec1
$x0 = COPY %smin
RET_ReallyLR implicit $x0
...
---
name: v16s8_smin
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v16s8_smin
; CHECK: liveins: $q0
; CHECK: %vec:_(<16 x s8>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF
; CHECK: %smin:_(<16 x s8>) = G_SMIN %vec, %vec1
; CHECK: $q0 = COPY %smin(<16 x s8>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<16 x s8>) = G_IMPLICIT_DEF
%vec1:_(<16 x s8>) = G_IMPLICIT_DEF
%smin:_(<16 x s8>) = G_SMIN %vec, %vec1
$q0 = COPY %smin
RET_ReallyLR implicit $q0
...
---
name: v4s16_smin
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: v4s16_smin
; CHECK: liveins: $x0
; CHECK: %vec:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF
; CHECK: %smin:_(<4 x s16>) = G_SMIN %vec, %vec1
; CHECK: $x0 = COPY %smin(<4 x s16>)
; CHECK: RET_ReallyLR implicit $x0
%vec:_(<4 x s16>) = G_IMPLICIT_DEF
%vec1:_(<4 x s16>) = G_IMPLICIT_DEF
%smin:_(<4 x s16>) = G_SMIN %vec, %vec1
$x0 = COPY %smin
RET_ReallyLR implicit $x0
...
---
name: v8s16_smin
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v8s16_smin
; CHECK: liveins: $q0
; CHECK: %vec:_(<8 x s16>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF
; CHECK: %smin:_(<8 x s16>) = G_SMIN %vec, %vec1
; CHECK: $q0 = COPY %smin(<8 x s16>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<8 x s16>) = G_IMPLICIT_DEF
%vec1:_(<8 x s16>) = G_IMPLICIT_DEF
%smin:_(<8 x s16>) = G_SMIN %vec, %vec1
$q0 = COPY %smin
RET_ReallyLR implicit $q0
...
---
name: v2s32_smin
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0
; CHECK-LABEL: name: v2s32_smin
; CHECK: liveins: $x0
; CHECK: %vec:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK: %smin:_(<2 x s32>) = G_SMIN %vec, %vec1
; CHECK: $x0 = COPY %smin(<2 x s32>)
; CHECK: RET_ReallyLR implicit $x0
%vec:_(<2 x s32>) = G_IMPLICIT_DEF
%vec1:_(<2 x s32>) = G_IMPLICIT_DEF
%smin:_(<2 x s32>) = G_SMIN %vec, %vec1
$x0 = COPY %smin
RET_ReallyLR implicit $x0
...
---
name: v4s32_smin
tracksRegLiveness: true
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v4s32_smin
; CHECK: liveins: $q0
; CHECK: %vec:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF
; CHECK: %smin:_(<4 x s32>) = G_SMIN %vec, %vec1
; CHECK: $q0 = COPY %smin(<4 x s32>)
; CHECK: RET_ReallyLR implicit $q0
%vec:_(<4 x s32>) = G_IMPLICIT_DEF
%vec1:_(<4 x s32>) = G_IMPLICIT_DEF
%smin:_(<4 x s32>) = G_SMIN %vec, %vec1
$q0 = COPY %smin
RET_ReallyLR implicit $q0
...