forked from OSchip/llvm-project
[X86][SSE] Don't bother re-adding combined target shuffles to the work list
We are re-adding all the bitcasts, constant masks and target shuffles to the work list for no apparent gain. Found while investigating adding SimplifyDemandedVectorElts to target shuffles. Differential Revision: https://reviews.llvm.org/D44942 llvm-svn: 328771
This commit is contained in:
Simon Pilgrim
parent
47381fa611
commit
71c5f3fffd
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@ -29050,7 +29050,6 @@ static bool matchBinaryPermuteVectorShuffle(
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static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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ArrayRef<int> BaseMask, int Depth,
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bool HasVariableMask, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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assert(!BaseMask.empty() && "Cannot combine an empty shuffle mask!");
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assert((Inputs.size() == 1 || Inputs.size() == 2) &&
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@ -29112,11 +29111,9 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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PermMask |= ((BaseMask[1] < 0 ? 0x8 : (BaseMask[1] & 1)) << 4);
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Res = DAG.getBitcast(ShuffleVT, V1);
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DCI.AddToWorklist(Res.getNode());
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Res = DAG.getNode(X86ISD::VPERM2X128, DL, ShuffleVT, Res,
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DAG.getUNDEF(ShuffleVT),
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DAG.getConstant(PermMask, DL, MVT::i8));
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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@ -29182,9 +29179,7 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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if (Depth == 1 && Root.getOpcode() == Shuffle)
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return SDValue(); // Nothing to do!
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Res = DAG.getBitcast(ShuffleSrcVT, NewV1);
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DCI.AddToWorklist(Res.getNode());
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Res = DAG.getNode(Shuffle, DL, ShuffleVT, Res);
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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@ -29195,10 +29190,8 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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if (Depth == 1 && Root.getOpcode() == Shuffle)
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return SDValue(); // Nothing to do!
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Res = DAG.getBitcast(ShuffleVT, V1);
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DCI.AddToWorklist(Res.getNode());
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Res = DAG.getNode(Shuffle, DL, ShuffleVT, Res,
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DAG.getConstant(PermuteImm, DL, MVT::i8));
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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}
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@ -29212,11 +29205,8 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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if (Depth == 1 && Root.getOpcode() == Shuffle)
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return SDValue(); // Nothing to do!
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NewV1 = DAG.getBitcast(ShuffleSrcVT, NewV1);
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DCI.AddToWorklist(NewV1.getNode());
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NewV2 = DAG.getBitcast(ShuffleSrcVT, NewV2);
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DCI.AddToWorklist(NewV2.getNode());
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Res = DAG.getNode(Shuffle, DL, ShuffleVT, NewV1, NewV2);
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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@ -29229,12 +29219,9 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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if (Depth == 1 && Root.getOpcode() == Shuffle)
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return SDValue(); // Nothing to do!
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NewV1 = DAG.getBitcast(ShuffleVT, NewV1);
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DCI.AddToWorklist(NewV1.getNode());
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NewV2 = DAG.getBitcast(ShuffleVT, NewV2);
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DCI.AddToWorklist(NewV2.getNode());
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Res = DAG.getNode(Shuffle, DL, ShuffleVT, NewV1, NewV2,
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DAG.getConstant(PermuteImm, DL, MVT::i8));
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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@ -29250,11 +29237,9 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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if (Depth == 1 && Root.getOpcode() == X86ISD::EXTRQI)
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return SDValue(); // Nothing to do!
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V1 = DAG.getBitcast(IntMaskVT, V1);
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DCI.AddToWorklist(V1.getNode());
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Res = DAG.getNode(X86ISD::EXTRQI, DL, IntMaskVT, V1,
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DAG.getConstant(BitLen, DL, MVT::i8),
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DAG.getConstant(BitIdx, DL, MVT::i8));
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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@ -29262,13 +29247,10 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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if (Depth == 1 && Root.getOpcode() == X86ISD::INSERTQI)
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return SDValue(); // Nothing to do!
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V1 = DAG.getBitcast(IntMaskVT, V1);
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DCI.AddToWorklist(V1.getNode());
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V2 = DAG.getBitcast(IntMaskVT, V2);
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DCI.AddToWorklist(V2.getNode());
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Res = DAG.getNode(X86ISD::INSERTQI, DL, IntMaskVT, V1, V2,
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DAG.getConstant(BitLen, DL, MVT::i8),
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DAG.getConstant(BitIdx, DL, MVT::i8));
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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}
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@ -29298,11 +29280,8 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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(Subtarget.hasVBMI() && MaskVT == MVT::v64i8) ||
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(Subtarget.hasVBMI() && Subtarget.hasVLX() && MaskVT == MVT::v32i8))) {
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SDValue VPermMask = getConstVector(Mask, IntMaskVT, DAG, DL, true);
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DCI.AddToWorklist(VPermMask.getNode());
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Res = DAG.getBitcast(MaskVT, V1);
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DCI.AddToWorklist(Res.getNode());
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Res = DAG.getNode(X86ISD::VPERMV, DL, MaskVT, VPermMask, Res);
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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@ -29325,13 +29304,9 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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Mask[i] = NumMaskElts + i;
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SDValue VPermMask = getConstVector(Mask, IntMaskVT, DAG, DL, true);
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DCI.AddToWorklist(VPermMask.getNode());
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Res = DAG.getBitcast(MaskVT, V1);
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DCI.AddToWorklist(Res.getNode());
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SDValue Zero = getZeroVector(MaskVT, Subtarget, DAG, DL);
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DCI.AddToWorklist(Zero.getNode());
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Res = DAG.getNode(X86ISD::VPERMV3, DL, MaskVT, Res, VPermMask, Zero);
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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@ -29348,13 +29323,9 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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(Subtarget.hasVBMI() && MaskVT == MVT::v64i8) ||
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(Subtarget.hasVBMI() && Subtarget.hasVLX() && MaskVT == MVT::v32i8))) {
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SDValue VPermMask = getConstVector(Mask, IntMaskVT, DAG, DL, true);
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DCI.AddToWorklist(VPermMask.getNode());
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V1 = DAG.getBitcast(MaskVT, V1);
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DCI.AddToWorklist(V1.getNode());
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V2 = DAG.getBitcast(MaskVT, V2);
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DCI.AddToWorklist(V2.getNode());
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Res = DAG.getNode(X86ISD::VPERMV3, DL, MaskVT, V1, VPermMask, V2);
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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return SDValue();
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@ -29380,13 +29351,10 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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EltBits[i] = AllOnes;
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}
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SDValue BitMask = getConstVector(EltBits, UndefElts, MaskVT, DAG, DL);
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DCI.AddToWorklist(BitMask.getNode());
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Res = DAG.getBitcast(MaskVT, V1);
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DCI.AddToWorklist(Res.getNode());
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unsigned AndOpcode =
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FloatDomain ? unsigned(X86ISD::FAND) : unsigned(ISD::AND);
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Res = DAG.getNode(AndOpcode, DL, MaskVT, Res, BitMask);
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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@ -29403,11 +29371,8 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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VPermIdx.push_back(Idx);
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}
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SDValue VPermMask = DAG.getBuildVector(IntMaskVT, DL, VPermIdx);
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DCI.AddToWorklist(VPermMask.getNode());
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Res = DAG.getBitcast(MaskVT, V1);
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DCI.AddToWorklist(Res.getNode());
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Res = DAG.getNode(X86ISD::VPERMILPV, DL, MaskVT, Res, VPermMask);
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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@ -29439,14 +29404,10 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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VPerm2Idx.push_back(Index);
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}
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V1 = DAG.getBitcast(MaskVT, V1);
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DCI.AddToWorklist(V1.getNode());
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V2 = DAG.getBitcast(MaskVT, V2);
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DCI.AddToWorklist(V2.getNode());
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SDValue VPerm2MaskOp = getConstVector(VPerm2Idx, IntMaskVT, DAG, DL, true);
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DCI.AddToWorklist(VPerm2MaskOp.getNode());
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Res = DAG.getNode(X86ISD::VPERMIL2, DL, MaskVT, V1, V2, VPerm2MaskOp,
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DAG.getConstant(M2ZImm, DL, MVT::i8));
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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@ -29478,11 +29439,8 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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}
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MVT ByteVT = MVT::getVectorVT(MVT::i8, NumBytes);
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Res = DAG.getBitcast(ByteVT, V1);
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DCI.AddToWorklist(Res.getNode());
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SDValue PSHUFBMaskOp = DAG.getBuildVector(ByteVT, DL, PSHUFBMask);
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DCI.AddToWorklist(PSHUFBMaskOp.getNode());
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Res = DAG.getNode(X86ISD::PSHUFB, DL, ByteVT, Res, PSHUFBMaskOp);
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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@ -29511,13 +29469,9 @@ static SDValue combineX86ShuffleChain(ArrayRef<SDValue> Inputs, SDValue Root,
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}
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MVT ByteVT = MVT::v16i8;
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V1 = DAG.getBitcast(ByteVT, V1);
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DCI.AddToWorklist(V1.getNode());
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V2 = DAG.getBitcast(ByteVT, V2);
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DCI.AddToWorklist(V2.getNode());
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SDValue VPPERMMaskOp = DAG.getBuildVector(ByteVT, DL, VPPERMMask);
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DCI.AddToWorklist(VPPERMMaskOp.getNode());
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Res = DAG.getNode(X86ISD::VPPERM, DL, ByteVT, V1, V2, VPPERMMaskOp);
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DCI.AddToWorklist(Res.getNode());
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return DAG.getBitcast(RootVT, Res);
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}
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@ -29532,7 +29486,6 @@ static SDValue combineX86ShufflesConstants(const SmallVectorImpl<SDValue> &Ops,
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ArrayRef<int> Mask, SDValue Root,
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bool HasVariableMask,
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SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI,
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const X86Subtarget &Subtarget) {
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MVT VT = Root.getSimpleValueType();
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@ -29608,7 +29561,6 @@ static SDValue combineX86ShufflesConstants(const SmallVectorImpl<SDValue> &Ops,
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SDLoc DL(Root);
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SDValue CstOp = getConstVector(ConstantBitData, UndefElts, MaskVT, DAG, DL);
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DCI.AddToWorklist(CstOp.getNode());
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return DAG.getBitcast(VT, CstOp);
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}
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@ -29644,8 +29596,7 @@ static SDValue combineX86ShufflesConstants(const SmallVectorImpl<SDValue> &Ops,
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static SDValue combineX86ShufflesRecursively(
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ArrayRef<SDValue> SrcOps, int SrcOpIndex, SDValue Root,
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ArrayRef<int> RootMask, ArrayRef<const SDNode *> SrcNodes, unsigned Depth,
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bool HasVariableMask, SelectionDAG &DAG,
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TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget &Subtarget) {
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bool HasVariableMask, SelectionDAG &DAG, const X86Subtarget &Subtarget) {
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// Bound the depth of our recursive combine because this is ultimately
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// quadratic in nature.
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const unsigned MaxRecursionDepth = 8;
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@ -29810,13 +29761,13 @@ static SDValue combineX86ShufflesRecursively(
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SDNode::areOnlyUsersOf(CombinedNodes, Ops[i].getNode()))
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if (SDValue Res = combineX86ShufflesRecursively(
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Ops, i, Root, Mask, CombinedNodes, Depth + 1, HasVariableMask,
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DAG, DCI, Subtarget))
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DAG, Subtarget))
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return Res;
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}
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// Attempt to constant fold all of the constant source ops.
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if (SDValue Cst = combineX86ShufflesConstants(
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Ops, Mask, Root, HasVariableMask, DAG, DCI, Subtarget))
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Ops, Mask, Root, HasVariableMask, DAG, Subtarget))
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return Cst;
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// We can only combine unary and binary shuffle mask cases.
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@ -29842,7 +29793,7 @@ static SDValue combineX86ShufflesRecursively(
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// Finally, try to combine into a single shuffle instruction.
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return combineX86ShuffleChain(Ops, Root, Mask, Depth, HasVariableMask, DAG,
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DCI, Subtarget);
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Subtarget);
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}
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/// \brief Get the PSHUF-style mask from PSHUF node.
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@ -30144,7 +30095,7 @@ static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG,
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DemandedMask[i] = i;
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if (SDValue Res = combineX86ShufflesRecursively(
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{BC}, 0, BC, DemandedMask, {}, /*Depth*/ 1,
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/*HasVarMask*/ false, DAG, DCI, Subtarget))
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/*HasVarMask*/ false, DAG, Subtarget))
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return DAG.getNode(X86ISD::VBROADCAST, DL, VT,
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DAG.getBitcast(SrcVT, Res));
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}
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@ -30723,7 +30674,7 @@ static SDValue combineShuffle(SDNode *N, SelectionDAG &DAG,
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// a particular chain.
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if (SDValue Res = combineX86ShufflesRecursively(
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{Op}, 0, Op, {0}, {}, /*Depth*/ 1,
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/*HasVarMask*/ false, DAG, DCI, Subtarget)) {
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/*HasVarMask*/ false, DAG, Subtarget)) {
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DCI.CombineTo(N, Res);
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return SDValue();
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}
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@ -33548,9 +33499,9 @@ static SDValue combineVectorPack(SDNode *N, SelectionDAG &DAG,
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// Attempt to combine as shuffle.
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SDValue Op(N, 0);
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if (SDValue Res = combineX86ShufflesRecursively(
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{Op}, 0, Op, {0}, {}, /*Depth*/ 1,
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/*HasVarMask*/ false, DAG, DCI, Subtarget)) {
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if (SDValue Res =
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combineX86ShufflesRecursively({Op}, 0, Op, {0}, {}, /*Depth*/ 1,
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/*HasVarMask*/ false, DAG, Subtarget)) {
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DCI.CombineTo(N, Res);
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return SDValue();
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}
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@ -33612,7 +33563,7 @@ static SDValue combineVectorShiftImm(SDNode *N, SelectionDAG &DAG,
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SDValue Op(N, 0);
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if (SDValue Res = combineX86ShufflesRecursively(
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{Op}, 0, Op, {0}, {}, /*Depth*/ 1,
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/*HasVarMask*/ false, DAG, DCI, Subtarget)) {
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/*HasVarMask*/ false, DAG, Subtarget)) {
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DCI.CombineTo(N, Res);
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return SDValue();
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}
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@ -33651,9 +33602,9 @@ static SDValue combineVectorInsert(SDNode *N, SelectionDAG &DAG,
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// Attempt to combine PINSRB/PINSRW patterns to a shuffle.
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SDValue Op(N, 0);
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if (SDValue Res = combineX86ShufflesRecursively(
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{Op}, 0, Op, {0}, {}, /*Depth*/ 1,
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/*HasVarMask*/ false, DAG, DCI, Subtarget)) {
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if (SDValue Res =
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combineX86ShufflesRecursively({Op}, 0, Op, {0}, {}, /*Depth*/ 1,
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/*HasVarMask*/ false, DAG, Subtarget)) {
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DCI.CombineTo(N, Res);
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return SDValue();
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}
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@ -34094,7 +34045,7 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
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SDValue Op(N, 0);
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if (SDValue Res = combineX86ShufflesRecursively(
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{Op}, 0, Op, {0}, {}, /*Depth*/ 1,
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/*HasVarMask*/ false, DAG, DCI, Subtarget)) {
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/*HasVarMask*/ false, DAG, Subtarget)) {
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DCI.CombineTo(N, Res);
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return SDValue();
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}
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@ -34133,7 +34084,7 @@ static SDValue combineAnd(SDNode *N, SelectionDAG &DAG,
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if (SDValue Shuffle = combineX86ShufflesRecursively(
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{SrcVec}, 0, SrcVec, ShuffleMask, {}, /*Depth*/ 2,
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/*HasVarMask*/ false, DAG, DCI, Subtarget))
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/*HasVarMask*/ false, DAG, Subtarget))
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(N), VT, Shuffle,
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N->getOperand(0).getOperand(1));
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}
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@ -36414,7 +36365,7 @@ static SDValue combineAndnp(SDNode *N, SelectionDAG &DAG,
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SDValue Op(N, 0);
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if (SDValue Res = combineX86ShufflesRecursively(
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{Op}, 0, Op, {0}, {}, /*Depth*/ 1,
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/*HasVarMask*/ false, DAG, DCI, Subtarget)) {
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/*HasVarMask*/ false, DAG, Subtarget)) {
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DCI.CombineTo(N, Res);
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return SDValue();
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}
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