forked from OSchip/llvm-project
Revert "[LLDB] Arm64/Linux Add MTE and Pointer Authentication registers"
This reverts commit 1164b4e295.
Reason: LLDB AArch64 Linux buildbot failure
This commit is contained in:
Muhammad Omair Javaid
parent
feb6f2c78f
commit
71b648f715
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@ -33,17 +33,6 @@
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#define NT_ARM_SVE 0x405 /* ARM Scalable Vector Extension */
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#endif
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#ifndef NT_ARM_PAC_MASK
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#define NT_ARM_PAC_MASK 0x406 /* Pointer authentication code masks */
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#endif
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#ifndef NT_ARM_TAGGED_ADDR_CTRL
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#define NT_ARM_TAGGED_ADDR_CTRL 0x409 /* Tagged address control register */
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#endif
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#define HWCAP_PACA (1 << 30)
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#define HWCAP2_MTE (1 << 18)
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#define REG_CONTEXT_SIZE (GetGPRSize() + GetFPRSize())
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using namespace lldb;
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@ -73,18 +62,6 @@ NativeRegisterContextLinux::CreateHostNativeRegisterContextLinux(
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.Success())
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opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskSVE);
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NativeProcessLinux &process = native_thread.GetProcess();
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llvm::Optional<uint64_t> auxv_at_hwcap =
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process.GetAuxValue(AuxVector::AUXV_AT_HWCAP);
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if (auxv_at_hwcap && (*auxv_at_hwcap & HWCAP_PACA))
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opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskPAuth);
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llvm::Optional<uint64_t> auxv_at_hwcap2 =
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process.GetAuxValue(AuxVector::AUXV_AT_HWCAP2);
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if (auxv_at_hwcap && (*auxv_at_hwcap2 & HWCAP2_MTE))
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opt_regsets.Set(RegisterInfoPOSIX_arm64::eRegsetMaskMTE);
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auto register_info_up =
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std::make_unique<RegisterInfoPOSIX_arm64>(target_arch, opt_regsets);
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return std::make_unique<NativeRegisterContextLinux_arm64>(
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@ -105,9 +82,6 @@ NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64(
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::memset(&m_hwp_regs, 0, sizeof(m_hwp_regs));
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::memset(&m_hbp_regs, 0, sizeof(m_hbp_regs));
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::memset(&m_sve_header, 0, sizeof(m_sve_header));
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::memset(&m_pac_mask, 0, sizeof(m_pac_mask));
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m_mte_ctrl_reg = 0;
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// 16 is just a maximum value, query hardware for actual watchpoint count
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m_max_hwp_supported = 16;
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@ -119,8 +93,6 @@ NativeRegisterContextLinux_arm64::NativeRegisterContextLinux_arm64(
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m_fpu_is_valid = false;
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m_sve_buffer_is_valid = false;
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m_sve_header_is_valid = false;
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m_pac_mask_is_valid = false;
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m_mte_ctrl_is_valid = false;
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if (GetRegisterInfo().IsSVEEnabled())
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m_sve_state = SVEState::Unknown;
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@ -257,22 +229,6 @@ NativeRegisterContextLinux_arm64::ReadRegister(const RegisterInfo *reg_info,
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src = (uint8_t *)GetSVEBuffer() + offset;
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}
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}
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} else if (IsPAuth(reg)) {
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error = ReadPAuthMask();
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if (error.Fail())
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return error;
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offset = reg_info->byte_offset - GetRegisterInfo().GetPAuthOffset();
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assert(offset < GetPACMaskSize());
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src = (uint8_t *)GetPACMask() + offset;
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} else if (IsMTE(reg)) {
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error = ReadMTEControl();
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if (error.Fail())
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return error;
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offset = reg_info->byte_offset - GetRegisterInfo().GetMTEOffset();
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assert(offset < GetMTEControlSize());
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src = (uint8_t *)GetMTEControl() + offset;
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} else
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return Status("failed - register wasn't recognized to be a GPR or an FPR, "
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"write strategy unknown");
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@ -431,17 +387,6 @@ Status NativeRegisterContextLinux_arm64::WriteRegister(
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return WriteAllSVE();
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}
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}
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} else if (IsMTE(reg)) {
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error = ReadMTEControl();
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if (error.Fail())
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return error;
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offset = reg_info->byte_offset - GetRegisterInfo().GetMTEOffset();
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assert(offset < GetMTEControlSize());
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dst = (uint8_t *)GetMTEControl() + offset;
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::memcpy(dst, reg_value.GetBytes(), reg_info->byte_size);
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return WriteMTEControl();
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}
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return Status("Failed to write register value");
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@ -530,14 +475,6 @@ bool NativeRegisterContextLinux_arm64::IsSVE(unsigned reg) const {
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return GetRegisterInfo().IsSVEReg(reg);
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}
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bool NativeRegisterContextLinux_arm64::IsPAuth(unsigned reg) const {
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return GetRegisterInfo().IsPAuthReg(reg);
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}
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bool NativeRegisterContextLinux_arm64::IsMTE(unsigned reg) const {
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return GetRegisterInfo().IsMTEReg(reg);
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}
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llvm::Error NativeRegisterContextLinux_arm64::ReadHardwareDebugInfo() {
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if (!m_refresh_hwdebug_info) {
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return llvm::Error::success();
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@ -679,8 +616,6 @@ void NativeRegisterContextLinux_arm64::InvalidateAllRegisters() {
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m_fpu_is_valid = false;
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m_sve_buffer_is_valid = false;
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m_sve_header_is_valid = false;
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m_pac_mask_is_valid = false;
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m_mte_ctrl_is_valid = false;
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// Update SVE registers in case there is change in configuration.
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ConfigureRegisterContext();
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@ -698,26 +633,7 @@ Status NativeRegisterContextLinux_arm64::ReadSVEHeader() {
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error = ReadRegisterSet(&ioVec, GetSVEHeaderSize(), NT_ARM_SVE);
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if (error.Success())
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m_sve_header_is_valid = true;
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return error;
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}
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Status NativeRegisterContextLinux_arm64::ReadPAuthMask() {
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Status error;
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if (m_pac_mask_is_valid)
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return error;
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struct iovec ioVec;
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ioVec.iov_base = GetPACMask();
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ioVec.iov_len = GetPACMaskSize();
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error = ReadRegisterSet(&ioVec, GetPACMaskSize(), NT_ARM_PAC_MASK);
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if (error.Success())
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m_pac_mask_is_valid = true;
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m_sve_header_is_valid = true;
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return error;
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}
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@ -777,40 +693,6 @@ Status NativeRegisterContextLinux_arm64::WriteAllSVE() {
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return WriteRegisterSet(&ioVec, GetSVEBufferSize(), NT_ARM_SVE);
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}
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Status NativeRegisterContextLinux_arm64::ReadMTEControl() {
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Status error;
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if (m_mte_ctrl_is_valid)
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return error;
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struct iovec ioVec;
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ioVec.iov_base = GetMTEControl();
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ioVec.iov_len = GetMTEControlSize();
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error = ReadRegisterSet(&ioVec, GetMTEControlSize(), NT_ARM_TAGGED_ADDR_CTRL);
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if (error.Success())
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m_mte_ctrl_is_valid = true;
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return error;
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}
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Status NativeRegisterContextLinux_arm64::WriteMTEControl() {
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Status error;
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error = ReadMTEControl();
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if (error.Fail())
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return error;
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struct iovec ioVec;
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ioVec.iov_base = GetMTEControl();
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ioVec.iov_len = GetMTEControlSize();
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m_mte_ctrl_is_valid = false;
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return WriteRegisterSet(&ioVec, GetMTEControlSize(), NT_ARM_TAGGED_ADDR_CTRL);
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}
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void NativeRegisterContextLinux_arm64::ConfigureRegisterContext() {
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// ConfigureRegisterContext gets called from InvalidateAllRegisters
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// on every stop and configures SVE vector length.
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@ -76,10 +76,8 @@ private:
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bool m_gpr_is_valid;
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bool m_fpu_is_valid;
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bool m_sve_buffer_is_valid;
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bool m_mte_ctrl_is_valid;
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bool m_sve_header_is_valid;
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bool m_pac_mask_is_valid;
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struct user_pt_regs m_gpr_arm64; // 64-bit general purpose registers.
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@ -92,15 +90,6 @@ private:
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bool m_refresh_hwdebug_info;
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struct user_pac_mask {
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uint64_t data_mask;
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uint64_t insn_mask;
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};
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struct user_pac_mask m_pac_mask;
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uint64_t m_mte_ctrl_reg;
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bool IsGPR(unsigned reg) const;
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bool IsFPR(unsigned reg) const;
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@ -113,15 +102,7 @@ private:
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Status WriteSVEHeader();
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Status ReadPAuthMask();
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Status ReadMTEControl();
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Status WriteMTEControl();
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bool IsSVE(unsigned reg) const;
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bool IsPAuth(unsigned reg) const;
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bool IsMTE(unsigned reg) const;
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uint64_t GetSVERegVG() { return m_sve_header.vl / 8; }
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@ -129,20 +110,12 @@ private:
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void *GetSVEHeader() { return &m_sve_header; }
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void *GetPACMask() { return &m_pac_mask; }
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void *GetMTEControl() { return &m_mte_ctrl_reg; }
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void *GetSVEBuffer();
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size_t GetSVEHeaderSize() { return sizeof(m_sve_header); }
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size_t GetPACMaskSize() { return sizeof(m_pac_mask); }
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size_t GetSVEBufferSize() { return m_sve_ptrace_payload.size(); }
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size_t GetMTEControlSize() { return sizeof(m_mte_ctrl_reg); }
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llvm::Error ReadHardwareDebugInfo() override;
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llvm::Error WriteHardwareDebugRegs(DREGType hwbType) override;
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@ -53,8 +53,6 @@ public:
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Status RemoveHardwareBreakpoint(lldb::addr_t addr) override;
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NativeProcessLinux &GetProcess();
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private:
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// Interface for friend classes
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@ -96,6 +94,8 @@ private:
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// Private interface
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void MaybeLogStateChange(lldb::StateType new_state);
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NativeProcessLinux &GetProcess();
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void SetStopped();
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// Member Variables
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@ -21,9 +21,6 @@ namespace lldb_private {
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class NativeProcessELF : public NativeProcessProtocol {
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using NativeProcessProtocol::NativeProcessProtocol;
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public:
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llvm::Optional<uint64_t> GetAuxValue(enum AuxVector::EntryType type);
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protected:
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template <typename T> struct ELFLinkMap {
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T l_addr;
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@ -33,6 +30,8 @@ protected:
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T l_prev;
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};
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llvm::Optional<uint64_t> GetAuxValue(enum AuxVector::EntryType type);
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lldb::addr_t GetSharedLibraryInfoAddress() override;
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template <typename ELF_EHDR, typename ELF_PHDR, typename ELF_DYN>
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@ -77,8 +77,6 @@ enum {
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k_num_gpr_registers = gpr_w28 - gpr_x0 + 1,
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k_num_fpr_registers = fpu_fpcr - fpu_v0 + 1,
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k_num_sve_registers = sve_ffr - sve_vg + 1,
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k_num_mte_register = 1,
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k_num_pauth_register = 2,
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k_num_register_sets_default = 2,
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k_num_register_sets = 3
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};
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@ -177,12 +175,6 @@ static const lldb_private::RegisterSet g_reg_sets_arm64[k_num_register_sets] = {
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{"Scalable Vector Extension Registers", "sve", k_num_sve_registers,
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g_sve_regnums_arm64}};
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static const lldb_private::RegisterSet g_reg_set_pauth_arm64 = {
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"Pointer Authentication Registers", "pauth", k_num_pauth_register, NULL};
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static const lldb_private::RegisterSet g_reg_set_mte_arm64 = {
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"MTE Control Register", "mte", k_num_mte_register, NULL};
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RegisterInfoPOSIX_arm64::RegisterInfoPOSIX_arm64(
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const lldb_private::ArchSpec &target_arch, lldb_private::Flags opt_regsets)
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: lldb_private::RegisterInfoAndSetInterface(target_arch),
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@ -217,12 +209,6 @@ RegisterInfoPOSIX_arm64::RegisterInfoPOSIX_arm64(
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llvm::copy(reg_infos_ref, std::back_inserter(m_dynamic_reg_infos));
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llvm::copy(reg_sets_ref, std::back_inserter(m_dynamic_reg_sets));
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if (m_opt_regsets.AllSet(eRegsetMaskPAuth))
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AddRegSetPAuth();
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if (m_opt_regsets.AllSet(eRegsetMaskMTE))
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AddRegSetMTE();
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m_register_info_count = m_dynamic_reg_infos.size();
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m_register_info_p = m_dynamic_reg_infos.data();
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m_register_set_p = m_dynamic_reg_sets.data();
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@ -273,39 +259,6 @@ RegisterInfoPOSIX_arm64::GetRegisterSet(size_t set_index) const {
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return nullptr;
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}
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void RegisterInfoPOSIX_arm64::AddRegSetPAuth() {
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uint32_t pa_regnum = m_dynamic_reg_infos.size();
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for (uint32_t i = 0; i < k_num_pauth_register; i++) {
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pauth_regnum_collection.push_back(pa_regnum + i);
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m_dynamic_reg_infos.push_back(g_register_infos_pauth[i]);
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m_dynamic_reg_infos[pa_regnum + i].byte_offset =
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m_dynamic_reg_infos[pa_regnum + i - 1].byte_offset +
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m_dynamic_reg_infos[pa_regnum + i - 1].byte_size;
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m_dynamic_reg_infos[pa_regnum + i].kinds[lldb::eRegisterKindLLDB] =
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pa_regnum + i;
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}
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m_per_regset_regnum_range[m_register_set_count] =
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std::make_pair(pa_regnum, m_dynamic_reg_infos.size());
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m_dynamic_reg_sets.push_back(g_reg_set_pauth_arm64);
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m_dynamic_reg_sets.back().registers = pauth_regnum_collection.data();
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}
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void RegisterInfoPOSIX_arm64::AddRegSetMTE() {
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uint32_t mte_regnum = m_dynamic_reg_infos.size();
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m_mte_regnum_collection.push_back(mte_regnum);
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m_dynamic_reg_infos.push_back(g_register_infos_mte[0]);
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m_dynamic_reg_infos[mte_regnum].byte_offset =
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m_dynamic_reg_infos[mte_regnum - 1].byte_offset +
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m_dynamic_reg_infos[mte_regnum - 1].byte_size;
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m_dynamic_reg_infos[mte_regnum].kinds[lldb::eRegisterKindLLDB] = mte_regnum;
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m_per_regset_regnum_range[m_register_set_count] =
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std::make_pair(mte_regnum, mte_regnum + 1);
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m_dynamic_reg_sets.push_back(g_reg_set_mte_arm64);
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m_dynamic_reg_sets.back().registers = m_mte_regnum_collection.data();
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}
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uint32_t RegisterInfoPOSIX_arm64::ConfigureVectorLength(uint32_t sve_vq) {
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// sve_vq contains SVE Quad vector length in context of AArch64 SVE.
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// SVE register infos if enabled cannot be disabled by selecting sve_vq = 0.
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@ -389,18 +342,6 @@ bool RegisterInfoPOSIX_arm64::IsSVERegVG(unsigned reg) const {
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return sve_vg == reg;
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}
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bool RegisterInfoPOSIX_arm64::IsPAuthReg(unsigned reg) const {
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return std::find(pauth_regnum_collection.begin(),
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pauth_regnum_collection.end(),
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reg) != pauth_regnum_collection.end();
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}
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bool RegisterInfoPOSIX_arm64::IsMTEReg(unsigned reg) const {
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return std::find(m_mte_regnum_collection.begin(),
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m_mte_regnum_collection.end(),
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reg) != m_mte_regnum_collection.end();
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}
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uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEZ0() const { return sve_z0; }
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uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEFFR() const { return sve_ffr; }
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@ -410,11 +351,3 @@ uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPCR() const { return fpu_fpcr; }
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uint32_t RegisterInfoPOSIX_arm64::GetRegNumFPSR() const { return fpu_fpsr; }
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uint32_t RegisterInfoPOSIX_arm64::GetRegNumSVEVG() const { return sve_vg; }
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uint32_t RegisterInfoPOSIX_arm64::GetPAuthOffset() const {
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return m_register_info_p[pauth_regnum_collection[0]].byte_offset;
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}
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uint32_t RegisterInfoPOSIX_arm64::GetMTEOffset() const {
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return m_register_info_p[m_mte_regnum_collection[0]].byte_offset;
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}
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@ -26,8 +26,6 @@ public:
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enum {
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eRegsetMaskDefault = 0,
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eRegsetMaskSVE = 1,
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eRegsetMaskPAuth = 2,
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eRegsetMaskMTE = 4,
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eRegsetMaskDynamic = ~1,
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};
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@ -96,10 +94,6 @@ public:
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size_t GetRegisterSetFromRegisterIndex(uint32_t reg_index) const override;
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void AddRegSetPAuth();
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void AddRegSetMTE();
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uint32_t ConfigureVectorLength(uint32_t sve_vq);
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bool VectorSizeIsValid(uint32_t vq) {
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@ -114,16 +108,12 @@ public:
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bool IsSVEZReg(unsigned reg) const;
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||||
bool IsSVEPReg(unsigned reg) const;
|
||||
bool IsSVERegVG(unsigned reg) const;
|
||||
bool IsPAuthReg(unsigned reg) const;
|
||||
bool IsMTEReg(unsigned reg) const;
|
||||
|
||||
uint32_t GetRegNumSVEZ0() const;
|
||||
uint32_t GetRegNumSVEFFR() const;
|
||||
uint32_t GetRegNumFPCR() const;
|
||||
uint32_t GetRegNumFPSR() const;
|
||||
uint32_t GetRegNumSVEVG() const;
|
||||
uint32_t GetPAuthOffset() const;
|
||||
uint32_t GetMTEOffset() const;
|
||||
|
||||
private:
|
||||
typedef std::map<uint32_t, std::vector<lldb_private::RegisterInfo>>
|
||||
|
|
@ -147,9 +137,6 @@ private:
|
|||
|
||||
std::vector<lldb_private::RegisterInfo> m_dynamic_reg_infos;
|
||||
std::vector<lldb_private::RegisterSet> m_dynamic_reg_sets;
|
||||
|
||||
std::vector<uint32_t> pauth_regnum_collection;
|
||||
std::vector<uint32_t> m_mte_regnum_collection;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -470,13 +470,6 @@ static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
|
|||
LLDB_INVALID_REGNUM, lldb_kind \
|
||||
}
|
||||
|
||||
// Generates register kinds array for registers with only lldb kind
|
||||
#define KIND_ALL_INVALID \
|
||||
{ \
|
||||
LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \
|
||||
LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM \
|
||||
}
|
||||
|
||||
// Generates register kinds array for vector registers
|
||||
#define GPR64_KIND(reg, generic_kind) MISC_KIND(reg, gpr, generic_kind)
|
||||
#define VREG_KIND(reg) MISC_KIND(reg, fpu, LLDB_INVALID_REGNUM)
|
||||
|
|
@ -533,13 +526,6 @@ static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM};
|
|||
nullptr, 0 \
|
||||
}
|
||||
|
||||
// Defines pointer authentication mask registers
|
||||
#define DEFINE_EXTENSION_REG(reg) \
|
||||
{ \
|
||||
#reg, nullptr, 8, 0, lldb::eEncodingUint, lldb::eFormatHex, \
|
||||
KIND_ALL_INVALID, nullptr, nullptr, nullptr, 0 \
|
||||
}
|
||||
|
||||
static lldb_private::RegisterInfo g_register_infos_arm64_le[] = {
|
||||
// DEFINE_GPR64(name, GENERIC KIND)
|
||||
DEFINE_GPR64(x0, LLDB_REGNUM_GENERIC_ARG1),
|
||||
|
|
@ -786,12 +772,7 @@ static lldb_private::RegisterInfo g_register_infos_arm64_le[] = {
|
|||
{DEFINE_DBG(wcr, 13)},
|
||||
{DEFINE_DBG(wcr, 14)},
|
||||
{DEFINE_DBG(wcr, 15)}
|
||||
// clang-format on
|
||||
};
|
||||
// clang-format on
|
||||
static lldb_private::RegisterInfo g_register_infos_pauth[] = {
|
||||
DEFINE_EXTENSION_REG(data_mask), DEFINE_EXTENSION_REG(code_mask)};
|
||||
|
||||
static lldb_private::RegisterInfo g_register_infos_mte[] = {
|
||||
DEFINE_EXTENSION_REG(mte_ctrl)};
|
||||
|
||||
#endif // DECLARE_REGISTER_INFOS_ARM64_STRUCT
|
||||
|
|
|
|||
Loading…
Reference in New Issue