forked from OSchip/llvm-project
R600/SI: Implement fp32<->fp64 conversions
llvm-svn: 187988
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@ -85,6 +85,9 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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setLoadExtAction(ISD::SEXTLOAD, MVT::i32, Expand);
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setTargetDAGCombine(ISD::SELECT_CC);
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@ -625,8 +625,12 @@ defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>;
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//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
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//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
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//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
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//defm V_CVT_F32_F64 : VOP1_32 <0x0000000f, "V_CVT_F32_F64", []>;
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//defm V_CVT_F64_F32 : VOP1_64 <0x00000010, "V_CVT_F64_F32", []>;
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defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64",
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[(set f32:$dst, (fround f64:$src0))]
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>;
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defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32",
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[(set f64:$dst, (fextend f32:$src0))]
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>;
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//defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>;
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//defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>;
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//defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>;
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@ -0,0 +1,9 @@
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK
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; CHECK: @fpext
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; CHECK: V_CVT_F64_F32_e32
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define void @fpext(double addrspace(1)* %out, float %in) {
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%result = fpext float %in to double
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store double %result, double addrspace(1)* %out
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ret void
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}
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@ -0,0 +1,9 @@
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; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=CHECK
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; CHECK: @fptrunc
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; CHECK: V_CVT_F32_F64_e32
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define void @fptrunc(float addrspace(1)* %out, double %in) {
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%result = fptrunc double %in to float
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store float %result, float addrspace(1)* %out
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ret void
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}
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