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[ARM] Formatting for ARMInstrMVE.td. NFC 

This is just some formatting cleanup, prior to the masked load and store patch
in D66534.

llvm-svn: 369545
This commit is contained in:
David Green 2019-08-21 16:20:35 +00:00
parent f3b179589e
commit 717feabdf0
1 changed files with 96 additions and 87 deletions
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183
llvm/lib/Target/ARM/ARMInstrMVE.td
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@ -4802,59 +4802,60 @@ def MVE_LCTP : MVE_loltp_end<(outs), (ins pred:$p), "lctp${p}", ""> {
// Patterns
//===----------------------------------------------------------------------===//
class MVE_unpred_vector_store_typed<ValueType Ty, Instruction RegImmInst,
class MVE_vector_store_typed<ValueType Ty, Instruction RegImmInst,
PatFrag StoreKind, int shift>
: Pat<(StoreKind (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr),
(RegImmInst (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr)>;
multiclass MVE_vector_store<Instruction RegImmInst, PatFrag StoreKind,
int shift> {
def : MVE_vector_store_typed<v16i8, RegImmInst, StoreKind, shift>;
def : MVE_vector_store_typed<v8i16, RegImmInst, StoreKind, shift>;
def : MVE_vector_store_typed<v8f16, RegImmInst, StoreKind, shift>;
def : MVE_vector_store_typed<v4i32, RegImmInst, StoreKind, shift>;
def : MVE_vector_store_typed<v4f32, RegImmInst, StoreKind, shift>;
def : MVE_vector_store_typed<v2i64, RegImmInst, StoreKind, shift>;
def : MVE_vector_store_typed<v2f64, RegImmInst, StoreKind, shift>;
}
class MVE_vector_load_typed<ValueType Ty, Instruction RegImmInst,
PatFrag LoadKind, int shift>
: Pat<(Ty (LoadKind t2addrmode_imm7<shift>:$addr)),
(Ty (RegImmInst t2addrmode_imm7<shift>:$addr))>;
multiclass MVE_vector_load<Instruction RegImmInst, PatFrag LoadKind,
int shift> {
def : MVE_vector_load_typed<v16i8, RegImmInst, LoadKind, shift>;
def : MVE_vector_load_typed<v8i16, RegImmInst, LoadKind, shift>;
def : MVE_vector_load_typed<v8f16, RegImmInst, LoadKind, shift>;
def : MVE_vector_load_typed<v4i32, RegImmInst, LoadKind, shift>;
def : MVE_vector_load_typed<v4f32, RegImmInst, LoadKind, shift>;
def : MVE_vector_load_typed<v2i64, RegImmInst, LoadKind, shift>;
def : MVE_vector_load_typed<v2f64, RegImmInst, LoadKind, shift>;
}
class MVE_vector_offset_store_typed<ValueType Ty, Instruction Opcode,
PatFrag StoreKind, int shift>
: Pat<(StoreKind (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr),
(RegImmInst (Ty MQPR:$val), t2addrmode_imm7<shift>:$addr)>;
: Pat<(StoreKind (Ty MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<shift>:$addr),
(Opcode MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<shift>:$addr)>;
multiclass MVE_unpred_vector_store<Instruction RegImmInst, PatFrag StoreKind,
multiclass MVE_vector_offset_store<Instruction RegImmInst, PatFrag StoreKind,
int shift> {
def : MVE_unpred_vector_store_typed<v16i8, RegImmInst, StoreKind, shift>;
def : MVE_unpred_vector_store_typed<v8i16, RegImmInst, StoreKind, shift>;
def : MVE_unpred_vector_store_typed<v8f16, RegImmInst, StoreKind, shift>;
def : MVE_unpred_vector_store_typed<v4i32, RegImmInst, StoreKind, shift>;
def : MVE_unpred_vector_store_typed<v4f32, RegImmInst, StoreKind, shift>;
def : MVE_unpred_vector_store_typed<v2i64, RegImmInst, StoreKind, shift>;
def : MVE_unpred_vector_store_typed<v2f64, RegImmInst, StoreKind, shift>;
def : MVE_vector_offset_store_typed<v16i8, RegImmInst, StoreKind, shift>;
def : MVE_vector_offset_store_typed<v8i16, RegImmInst, StoreKind, shift>;
def : MVE_vector_offset_store_typed<v8f16, RegImmInst, StoreKind, shift>;
def : MVE_vector_offset_store_typed<v4i32, RegImmInst, StoreKind, shift>;
def : MVE_vector_offset_store_typed<v4f32, RegImmInst, StoreKind, shift>;
def : MVE_vector_offset_store_typed<v2i64, RegImmInst, StoreKind, shift>;
def : MVE_vector_offset_store_typed<v2f64, RegImmInst, StoreKind, shift>;
}
class MVE_unpred_vector_load_typed<ValueType Ty, Instruction RegImmInst,
PatFrag LoadKind, int shift>
: Pat<(Ty (LoadKind t2addrmode_imm7<shift>:$addr)),
(Ty (RegImmInst t2addrmode_imm7<shift>:$addr))>;
multiclass MVE_unpred_vector_load<Instruction RegImmInst, PatFrag LoadKind,
int shift> {
def : MVE_unpred_vector_load_typed<v16i8, RegImmInst, LoadKind, shift>;
def : MVE_unpred_vector_load_typed<v8i16, RegImmInst, LoadKind, shift>;
def : MVE_unpred_vector_load_typed<v8f16, RegImmInst, LoadKind, shift>;
def : MVE_unpred_vector_load_typed<v4i32, RegImmInst, LoadKind, shift>;
def : MVE_unpred_vector_load_typed<v4f32, RegImmInst, LoadKind, shift>;
def : MVE_unpred_vector_load_typed<v2i64, RegImmInst, LoadKind, shift>;
def : MVE_unpred_vector_load_typed<v2f64, RegImmInst, LoadKind, shift>;
}
class MVE_unpred_vector_offset_store_typed<ValueType Ty, Instruction Opcode,
PatFrag StoreKind, int shift>
: Pat<(StoreKind (Ty MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<shift>:$addr),
(Opcode MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<shift>:$addr)>;
multiclass MVE_unpred_vector_offset_store<Instruction RegImmInst, PatFrag StoreKind,
int shift> {
def : MVE_unpred_vector_offset_store_typed<v16i8, RegImmInst, StoreKind, shift>;
def : MVE_unpred_vector_offset_store_typed<v8i16, RegImmInst, StoreKind, shift>;
def : MVE_unpred_vector_offset_store_typed<v8f16, RegImmInst, StoreKind, shift>;
def : MVE_unpred_vector_offset_store_typed<v4i32, RegImmInst, StoreKind, shift>;
def : MVE_unpred_vector_offset_store_typed<v4f32, RegImmInst, StoreKind, shift>;
def : MVE_unpred_vector_offset_store_typed<v2i64, RegImmInst, StoreKind, shift>;
def : MVE_unpred_vector_offset_store_typed<v2f64, RegImmInst, StoreKind, shift>;
}
def aligned32_pre_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
(pre_store node:$val, node:$ptr, node:$offset), [{
return cast<StoreSDNode>(N)->getAlignment() >= 4;
}]>;
def aligned32_post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
(post_store node:$val, node:$ptr, node:$offset), [{
(post_store node:$val, node:$ptr, node:$offset), [{
return cast<StoreSDNode>(N)->getAlignment() >= 4;
}]>;
def aligned16_pre_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
@ -4862,39 +4863,44 @@ def aligned16_pre_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
return cast<StoreSDNode>(N)->getAlignment() >= 2;
}]>;
def aligned16_post_store : PatFrag<(ops node:$val, node:$ptr, node:$offset),
(post_store node:$val, node:$ptr, node:$offset), [{
(post_store node:$val, node:$ptr, node:$offset), [{
return cast<StoreSDNode>(N)->getAlignment() >= 2;
}]>;
let Predicates = [HasMVEInt, IsLE] in {
defm : MVE_unpred_vector_store<MVE_VSTRBU8, byte_alignedstore, 0>;
defm : MVE_unpred_vector_store<MVE_VSTRHU16, hword_alignedstore, 1>;
defm : MVE_unpred_vector_store<MVE_VSTRWU32, alignedstore32, 2>;
// Stores
defm : MVE_vector_store<MVE_VSTRBU8, byte_alignedstore, 0>;
defm : MVE_vector_store<MVE_VSTRHU16, hword_alignedstore, 1>;
defm : MVE_vector_store<MVE_VSTRWU32, alignedstore32, 2>;
defm : MVE_unpred_vector_load<MVE_VLDRBU8, byte_alignedload, 0>;
defm : MVE_unpred_vector_load<MVE_VLDRHU16, hword_alignedload, 1>;
defm : MVE_unpred_vector_load<MVE_VLDRWU32, alignedload32, 2>;
// Loads
defm : MVE_vector_load<MVE_VLDRBU8, byte_alignedload, 0>;
defm : MVE_vector_load<MVE_VLDRHU16, hword_alignedload, 1>;
defm : MVE_vector_load<MVE_VLDRWU32, alignedload32, 2>;
defm : MVE_unpred_vector_offset_store<MVE_VSTRBU8_pre, pre_store, 0>;
defm : MVE_unpred_vector_offset_store<MVE_VSTRBU8_post, post_store, 0>;
defm : MVE_unpred_vector_offset_store<MVE_VSTRHU16_pre, aligned16_pre_store, 1>;
defm : MVE_unpred_vector_offset_store<MVE_VSTRHU16_post, aligned16_post_store, 1>;
defm : MVE_unpred_vector_offset_store<MVE_VSTRWU32_pre, aligned32_pre_store, 2>;
defm : MVE_unpred_vector_offset_store<MVE_VSTRWU32_post, aligned32_post_store, 2>;
// Pre/post inc stores
defm : MVE_vector_offset_store<MVE_VSTRBU8_pre, pre_store, 0>;
defm : MVE_vector_offset_store<MVE_VSTRBU8_post, post_store, 0>;
defm : MVE_vector_offset_store<MVE_VSTRHU16_pre, aligned16_pre_store, 1>;
defm : MVE_vector_offset_store<MVE_VSTRHU16_post, aligned16_post_store, 1>;
defm : MVE_vector_offset_store<MVE_VSTRWU32_pre, aligned32_pre_store, 2>;
defm : MVE_vector_offset_store<MVE_VSTRWU32_post, aligned32_post_store, 2>;
}
let Predicates = [HasMVEInt, IsBE] in {
def : MVE_unpred_vector_store_typed<v16i8, MVE_VSTRBU8, store, 0>;
def : MVE_unpred_vector_store_typed<v8i16, MVE_VSTRHU16, alignedstore16, 1>;
def : MVE_unpred_vector_store_typed<v8f16, MVE_VSTRHU16, alignedstore16, 1>;
def : MVE_unpred_vector_store_typed<v4i32, MVE_VSTRWU32, alignedstore32, 2>;
def : MVE_unpred_vector_store_typed<v4f32, MVE_VSTRWU32, alignedstore32, 2>;
// Aligned Stores
def : MVE_vector_store_typed<v16i8, MVE_VSTRBU8, store, 0>;
def : MVE_vector_store_typed<v8i16, MVE_VSTRHU16, alignedstore16, 1>;
def : MVE_vector_store_typed<v8f16, MVE_VSTRHU16, alignedstore16, 1>;
def : MVE_vector_store_typed<v4i32, MVE_VSTRWU32, alignedstore32, 2>;
def : MVE_vector_store_typed<v4f32, MVE_VSTRWU32, alignedstore32, 2>;
def : MVE_unpred_vector_load_typed<v16i8, MVE_VLDRBU8, load, 0>;
def : MVE_unpred_vector_load_typed<v8i16, MVE_VLDRHU16, alignedload16, 1>;
def : MVE_unpred_vector_load_typed<v8f16, MVE_VLDRHU16, alignedload16, 1>;
def : MVE_unpred_vector_load_typed<v4i32, MVE_VLDRWU32, alignedload32, 2>;
def : MVE_unpred_vector_load_typed<v4f32, MVE_VLDRWU32, alignedload32, 2>;
// Aligned Loads
def : MVE_vector_load_typed<v16i8, MVE_VLDRBU8, load, 0>;
def : MVE_vector_load_typed<v8i16, MVE_VLDRHU16, alignedload16, 1>;
def : MVE_vector_load_typed<v8f16, MVE_VLDRHU16, alignedload16, 1>;
def : MVE_vector_load_typed<v4i32, MVE_VLDRWU32, alignedload32, 2>;
def : MVE_vector_load_typed<v4f32, MVE_VLDRWU32, alignedload32, 2>;
// Other unaligned loads/stores need to go though a VREV
def : Pat<(v2f64 (load t2addrmode_imm7<0>:$addr)),
@ -4922,19 +4928,21 @@ let Predicates = [HasMVEInt, IsBE] in {
def : Pat<(store (v8f16 MQPR:$val), t2addrmode_imm7<0>:$addr),
(MVE_VSTRBU8 (MVE_VREV16_8 MQPR:$val), t2addrmode_imm7<0>:$addr)>;
def : MVE_unpred_vector_offset_store_typed<v16i8, MVE_VSTRBU8_pre, pre_store, 0>;
def : MVE_unpred_vector_offset_store_typed<v16i8, MVE_VSTRBU8_post, post_store, 0>;
def : MVE_unpred_vector_offset_store_typed<v8i16, MVE_VSTRHU16_pre, aligned16_pre_store, 1>;
def : MVE_unpred_vector_offset_store_typed<v8i16, MVE_VSTRHU16_post, aligned16_post_store, 1>;
def : MVE_unpred_vector_offset_store_typed<v8f16, MVE_VSTRHU16_pre, aligned16_pre_store, 1>;
def : MVE_unpred_vector_offset_store_typed<v8f16, MVE_VSTRHU16_post, aligned16_post_store, 1>;
def : MVE_unpred_vector_offset_store_typed<v4i32, MVE_VSTRWU32_pre, aligned32_pre_store, 2>;
def : MVE_unpred_vector_offset_store_typed<v4i32, MVE_VSTRWU32_post, aligned32_post_store, 2>;
def : MVE_unpred_vector_offset_store_typed<v4f32, MVE_VSTRWU32_pre, aligned32_pre_store, 2>;
def : MVE_unpred_vector_offset_store_typed<v4f32, MVE_VSTRWU32_post, aligned32_post_store, 2>;
// Pre/Post inc stores
def : MVE_vector_offset_store_typed<v16i8, MVE_VSTRBU8_pre, pre_store, 0>;
def : MVE_vector_offset_store_typed<v16i8, MVE_VSTRBU8_post, post_store, 0>;
def : MVE_vector_offset_store_typed<v8i16, MVE_VSTRHU16_pre, aligned16_pre_store, 1>;
def : MVE_vector_offset_store_typed<v8i16, MVE_VSTRHU16_post, aligned16_post_store, 1>;
def : MVE_vector_offset_store_typed<v8f16, MVE_VSTRHU16_pre, aligned16_pre_store, 1>;
def : MVE_vector_offset_store_typed<v8f16, MVE_VSTRHU16_post, aligned16_post_store, 1>;
def : MVE_vector_offset_store_typed<v4i32, MVE_VSTRWU32_pre, aligned32_pre_store, 2>;
def : MVE_vector_offset_store_typed<v4i32, MVE_VSTRWU32_post, aligned32_post_store, 2>;
def : MVE_vector_offset_store_typed<v4f32, MVE_VSTRWU32_pre, aligned32_pre_store, 2>;
def : MVE_vector_offset_store_typed<v4f32, MVE_VSTRWU32_post, aligned32_post_store, 2>;
}
let Predicates = [HasMVEInt] in {
// Predicate loads
def : Pat<(v16i1 (load t2addrmode_imm7<2>:$addr)),
(v16i1 (VLDR_P0_off t2addrmode_imm7<2>:$addr))>;
def : Pat<(v8i1 (load t2addrmode_imm7<2>:$addr)),
@ -4942,6 +4950,7 @@ let Predicates = [HasMVEInt] in {
def : Pat<(v4i1 (load t2addrmode_imm7<2>:$addr)),
(v4i1 (VLDR_P0_off t2addrmode_imm7<2>:$addr))>;
// Predicate stores
def : Pat<(store (v4i1 VCCR:$val), t2addrmode_imm7<2>:$addr),
(VSTR_P0_off VCCR:$val, t2addrmode_imm7<2>:$addr)>;
def : Pat<(store (v8i1 VCCR:$val), t2addrmode_imm7<2>:$addr),
@ -4963,26 +4972,26 @@ let MinAlignment = 2 in {
}
let Predicates = [HasMVEInt] in {
def : Pat<(truncstorevi8 (v8i16 MQPR:$val), t2addrmode_imm7<0>:$addr),
(MVE_VSTRB16 MQPR:$val, t2addrmode_imm7<0>:$addr)>;
def : Pat<(truncstorevi8 (v4i32 MQPR:$val), t2addrmode_imm7<0>:$addr),
(MVE_VSTRB32 MQPR:$val, t2addrmode_imm7<0>:$addr)>;
def : Pat<(truncstorevi8 (v8i16 MQPR:$val), t2addrmode_imm7<0>:$addr),
(MVE_VSTRB16 MQPR:$val, t2addrmode_imm7<0>:$addr)>;
def : Pat<(truncstorevi8 (v4i32 MQPR:$val), t2addrmode_imm7<0>:$addr),
(MVE_VSTRB32 MQPR:$val, t2addrmode_imm7<0>:$addr)>;
def : Pat<(truncstorevi16_align2 (v4i32 MQPR:$val), t2addrmode_imm7<1>:$addr),
(MVE_VSTRH32 MQPR:$val, t2addrmode_imm7<1>:$addr)>;
(MVE_VSTRH32 MQPR:$val, t2addrmode_imm7<1>:$addr)>;
def : Pat<(post_truncstvi8 (v8i16 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<0>:$addr),
(MVE_VSTRB16_post MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
(MVE_VSTRB16_post MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
def : Pat<(post_truncstvi8 (v4i32 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<0>:$addr),
(MVE_VSTRB32_post MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
(MVE_VSTRB32_post MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
def : Pat<(post_truncstvi16_align2 (v4i32 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<1>:$addr),
(MVE_VSTRH32_post MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<1>:$addr)>;
(MVE_VSTRH32_post MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<1>:$addr)>;
def : Pat<(pre_truncstvi8 (v8i16 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<0>:$addr),
(MVE_VSTRB16_pre MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
(MVE_VSTRB16_pre MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
def : Pat<(pre_truncstvi8 (v4i32 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<0>:$addr),
(MVE_VSTRB32_pre MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
(MVE_VSTRB32_pre MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<0>:$addr)>;
def : Pat<(pre_truncstvi16_align2 (v4i32 MQPR:$Rt), tGPR:$Rn, t2am_imm7_offset<1>:$addr),
(MVE_VSTRH32_pre MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<1>:$addr)>;
(MVE_VSTRH32_pre MQPR:$Rt, tGPR:$Rn, t2am_imm7_offset<1>:$addr)>;
}