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ARM: update even more tests 

More updating of tests to be explicit about the target triple rather than
relying on the default target triple supporting ARM mode.

Indicate to lit that object emission is not yet available for Windows on ARM.

llvm-svn: 205545
This commit is contained in:
Saleem Abdulrasool 2014-04-03 17:35:22 +00:00
parent 2f4693aa77
commit 717c991923
10 changed files with 56 additions and 21 deletions
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2
llvm/test/CodeGen/ARM/argaddr.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm
; RUN: llc -mtriple=arm-eabi %s -o /dev/null
define void @f(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
entry:

2
llvm/test/CodeGen/ARM/movt.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=arm -mcpu=arm1156t2-s -mattr=+thumb2 | FileCheck %s
; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
; rdar://7317664
define i32 @t(i32 %X) nounwind {

14
llvm/test/CodeGen/ARM/mul.ll
View File

@ -1,11 +1,12 @@
; RUN: llc < %s -march=arm | grep mul | count 2
; RUN: llc < %s -march=arm | grep lsl | count 2
; RUN: llc -mtriple=arm-eabi %s -o - | FileCheck %s
define i32 @f1(i32 %u) {
%tmp = mul i32 %u, %u
ret i32 %tmp
}
; CHECK: mul
define i32 @f2(i32 %u, i32 %v) {
%tmp = mul i32 %u, %v
ret i32 %tmp
@ -16,7 +17,16 @@ define i32 @f3(i32 %u) {
ret i32 %tmp
}
; CHECK: mul
; CHECK: lsl
define i32 @f4(i32 %u) {
%tmp = mul i32 %u, 4
ret i32 %tmp
}
; CHECK-NOT: mul
; CHECK: lsl
; CHECK-NOT: lsl

2
llvm/test/CodeGen/ARM/ret_i64_arg2.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=arm -mattr=+vfp2 %s -o /dev/null
; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null
define i64 @test_i64(i64 %a1, i64 %a2) {
ret i64 %a2

2
llvm/test/CodeGen/ARM/ret_i64_arg3.ll
View File

@ -1,4 +1,4 @@
; RUN: llc -march=arm -mattr=+vfp2 %s -o /dev/null
; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o /dev/null
define i64 @test_i64_arg3(i64 %a1, i64 %a2, i64 %a3) {
ret i64 %a3

3
llvm/test/CodeGen/ARM/smml.ll
View File

@ -1,4 +1,5 @@
; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
define i32 @f(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
entry:
; CHECK-NOT: smmls

3
llvm/test/CodeGen/Thumb2/thumb2-select.ll
View File

@ -1,4 +1,5 @@
; RUN: llc < %s -march=thumb -mcpu=arm1156t2-s -mattr=+thumb2 -show-mc-encoding | FileCheck %s
; RUN: llc -mtriple=thumb-eabi -mcpu=arm1156t2-s -mattr=+thumb2 -show-mc-encoding %s -o - \
; RUN: | FileCheck %s
define i32 @f1(i32 %a.s) {
entry:

23
llvm/test/MC/ARM/arm-thumb-cpus-default.s
View File

@ -1,9 +1,20 @@
@ RUN: llvm-mc -show-encoding -arch=arm < %s | FileCheck %s --check-prefix=CHECK-ARM-ONLY
@ RUN: llvm-mc -show-encoding -triple=armv4t < %s | FileCheck %s --check-prefix=CHECK-ARM-THUMB
@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-a15 < %s| FileCheck %s --check-prefix=CHECK-ARM-THUMB
@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-m3 < %s | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
@ RUN: llvm-mc -show-encoding -triple=armv7m < %s | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
@ RUN: llvm-mc -show-encoding -triple=armv6m < %s | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
@ RUN: llvm-mc -show-encoding -triple=arm-eabi < %s \
@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-ONLY
@ RUN: llvm-mc -show-encoding -triple=armv4t-eabi < %s \
@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-THUMB
@ RUN: llvm-mc -show-encoding -triple=arm-eabi -mcpu=cortex-a15 < %s \
@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-THUMB
@ RUN: llvm-mc -show-encoding -triple=arm-eabi -mcpu=cortex-m3 < %s \
@ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
@ RUN: llvm-mc -show-encoding -triple=armv7m-eabi < %s \
@ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
@ RUN: llvm-mc -show-encoding -triple=armv6m-eabi < %s \
@ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
@ Make sure the architecture chosen by LLVM defaults to a compatible
@ ARM/Thumb mode.

23
llvm/test/MC/ARM/arm-thumb-cpus.s
View File

@ -1,9 +1,20 @@
@ RUN: not llvm-mc -show-encoding -arch=arm < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ARM-ONLY
@ RUN: llvm-mc -show-encoding -triple=armv4t < %s 2>&1| FileCheck %s --check-prefix=CHECK-ARM-THUMB
@ RUN: llvm-mc -show-encoding -arch=arm -mcpu=cortex-a15 < %s 2>&1| FileCheck %s --check-prefix=CHECK-ARM-THUMB
@ RUN: not llvm-mc -show-encoding -arch=arm -mcpu=cortex-m3 < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
@ RUN: not llvm-mc -show-encoding -triple=armv7m < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
@ RUN: not llvm-mc -show-encoding -triple=armv6m < %s 2>&1 | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
@ RUN: not llvm-mc -show-encoding -triple=arm-eabi < %s 2>&1 \
@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-ONLY
@ RUN: llvm-mc -show-encoding -triple=armv4t < %s 2>&1 \
@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-THUMB
@ RUN: llvm-mc -show-encoding -triple=arm-eabi -mcpu=cortex-a15 < %s 2>&1 \
@ RUN: | FileCheck %s --check-prefix=CHECK-ARM-THUMB
@ RUN: not llvm-mc -show-encoding -triple=arm-eabi -mcpu=cortex-m3 < %s 2>&1 \
@ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
@ RUN: not llvm-mc -show-encoding -triple=armv7m-eabi < %s 2>&1 \
@ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
@ RUN: not llvm-mc -show-encoding -triple=armv6m-eabi < %s 2>&1 \
@ RUN: | FileCheck %s --check-prefix=CHECK-THUMB-ONLY
@ Make sure correct diagnostics are given for CPUs without support for
@ one or other of the execution states.

3
llvm/test/lit.cfg
View File

@ -292,7 +292,8 @@ if (config.llvm_use_sanitizer == "Memory" or
config.available_features.add("msan")
# Direct object generation
if not 'hexagon' in config.target_triple:
if not 'hexagon' in config.target_triple and \
not re.match('(arm|thumb).*windows', config.target_triple):
config.available_features.add("object-emission")
if config.have_zlib == "1":