forked from OSchip/llvm-project
[AArch64][GlobalISel] Use the look-through constant helper for the shift s32->s64 custom legalization.
Almost NFC, except it catches more cases and gives a 0.1% CTMark -O0 size win.
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@ -756,16 +756,14 @@ bool AArch64LegalizerInfo::legalizeShlAshrLshr(
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// If the shift amount is a G_CONSTANT, promote it to a 64 bit type so the
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// imported patterns can select it later. Either way, it will be legal.
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Register AmtReg = MI.getOperand(2).getReg();
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auto *CstMI = MRI.getVRegDef(AmtReg);
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assert(CstMI && "expected to find a vreg def");
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if (CstMI->getOpcode() != TargetOpcode::G_CONSTANT)
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auto VRegAndVal = getConstantVRegValWithLookThrough(AmtReg, MRI);
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if (!VRegAndVal)
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return true;
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// Check the shift amount is in range for an immediate form.
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unsigned Amount = CstMI->getOperand(1).getCImm()->getZExtValue();
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int64_t Amount = VRegAndVal->Value;
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if (Amount > 31)
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return true; // This will have to remain a register variant.
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assert(MRI.getType(AmtReg).getSizeInBits() == 32);
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auto ExtCst = MIRBuilder.buildZExt(LLT::scalar(64), AmtReg);
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auto ExtCst = MIRBuilder.buildConstant(LLT::scalar(64), Amount);
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MI.getOperand(2).setReg(ExtCst.getReg(0));
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return true;
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}
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@ -24,9 +24,10 @@ body: |
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; CHECK-LABEL: name: test_unmerge_s4
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; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
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; CHECK: [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](s32)
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; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
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; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 4
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; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[UV]](s8)
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[C]](s32)
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; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
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; CHECK: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[ZEXT]], [[C1]](s64)
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; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[UV]](s8)
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; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32)
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; CHECK: $x0 = COPY [[ANYEXT]](s64)
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