forked from OSchip/llvm-project
Use COPY for extracting ImplicitDef'ed values from fast-isel instructions.
This assumes that the registers can be copied which is probably a safe assumption. llvm-svn: 108070
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@ -1077,11 +1077,8 @@ unsigned FastISel::FastEmitInst_r(unsigned MachineInstOpcode,
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else {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill);
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bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
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ResultReg, II.ImplicitDefs[0],
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RC, RC, DL);
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if (!InsertedCopy)
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ResultReg = 0;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(II.ImplicitDefs[0]);
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}
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return ResultReg;
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@ -1102,11 +1099,8 @@ unsigned FastISel::FastEmitInst_rr(unsigned MachineInstOpcode,
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addReg(Op1, Op1IsKill * RegState::Kill);
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bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
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ResultReg, II.ImplicitDefs[0],
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RC, RC, DL);
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if (!InsertedCopy)
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ResultReg = 0;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(II.ImplicitDefs[0]);
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}
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return ResultReg;
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}
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@ -1126,11 +1120,8 @@ unsigned FastISel::FastEmitInst_ri(unsigned MachineInstOpcode,
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addImm(Imm);
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bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
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ResultReg, II.ImplicitDefs[0],
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RC, RC, DL);
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if (!InsertedCopy)
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ResultReg = 0;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(II.ImplicitDefs[0]);
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}
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return ResultReg;
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}
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@ -1150,11 +1141,8 @@ unsigned FastISel::FastEmitInst_rf(unsigned MachineInstOpcode,
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addFPImm(FPImm);
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bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
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ResultReg, II.ImplicitDefs[0],
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RC, RC, DL);
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if (!InsertedCopy)
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ResultReg = 0;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(II.ImplicitDefs[0]);
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}
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return ResultReg;
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}
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@ -1177,11 +1165,8 @@ unsigned FastISel::FastEmitInst_rri(unsigned MachineInstOpcode,
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.addReg(Op0, Op0IsKill * RegState::Kill)
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.addReg(Op1, Op1IsKill * RegState::Kill)
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.addImm(Imm);
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bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
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ResultReg, II.ImplicitDefs[0],
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RC, RC, DL);
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if (!InsertedCopy)
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ResultReg = 0;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(II.ImplicitDefs[0]);
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}
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return ResultReg;
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}
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@ -1196,11 +1181,8 @@ unsigned FastISel::FastEmitInst_i(unsigned MachineInstOpcode,
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm);
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else {
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm);
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bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
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ResultReg, II.ImplicitDefs[0],
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RC, RC, DL);
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if (!InsertedCopy)
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ResultReg = 0;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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ResultReg).addReg(II.ImplicitDefs[0]);
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}
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return ResultReg;
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}
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