forked from OSchip/llvm-project
[AArch64] NFC: Refactoring to prepare for vector PCS.
This patch refactors several parts of AArch64FrameLowering so that it can be easily extended to support saving/restoring of FPR128 (Q) registers. Reviewers: t.p.northover, gberry, thegameg, rengolin, javed.absar Reviewed By: thegameg Differential Revision: https://reviews.llvm.org/D51478 llvm-svn: 342038
This commit is contained in:
Sander de Smalen
parent
386d272387
commit
7140363cd0
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@ -449,37 +449,37 @@ static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec(
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}
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unsigned NewOpc;
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bool NewIsUnscaled = false;
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int Scale = 1;
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switch (MBBI->getOpcode()) {
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default:
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llvm_unreachable("Unexpected callee-save save/restore opcode!");
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case AArch64::STPXi:
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NewOpc = AArch64::STPXpre;
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Scale = 8;
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break;
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case AArch64::STPDi:
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NewOpc = AArch64::STPDpre;
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Scale = 8;
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break;
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case AArch64::STRXui:
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NewOpc = AArch64::STRXpre;
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NewIsUnscaled = true;
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break;
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case AArch64::STRDui:
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NewOpc = AArch64::STRDpre;
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NewIsUnscaled = true;
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break;
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case AArch64::LDPXi:
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NewOpc = AArch64::LDPXpost;
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Scale = 8;
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break;
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case AArch64::LDPDi:
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NewOpc = AArch64::LDPDpost;
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Scale = 8;
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break;
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case AArch64::LDRXui:
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NewOpc = AArch64::LDRXpost;
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NewIsUnscaled = true;
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break;
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case AArch64::LDRDui:
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NewOpc = AArch64::LDRDpost;
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NewIsUnscaled = true;
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break;
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}
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@ -497,12 +497,8 @@ static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec(
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"instruction!");
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assert(MBBI->getOperand(OpndIdx - 1).getReg() == AArch64::SP &&
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"Unexpected base register in callee-save save/restore instruction!");
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// Last operand is immediate offset that needs fixing.
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assert(CSStackSizeInc % 8 == 0);
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int64_t CSStackSizeIncImm = CSStackSizeInc;
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if (!NewIsUnscaled)
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CSStackSizeIncImm /= 8;
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MIB.addImm(CSStackSizeIncImm);
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assert(CSStackSizeInc % Scale == 0);
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MIB.addImm(CSStackSizeInc / Scale);
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MIB.setMIFlags(MBBI->getFlags());
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MIB.setMemRefs(MBBI->memoperands());
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@ -523,12 +519,21 @@ static void fixupCalleeSaveRestoreStackOffset(MachineInstr &MI,
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return;
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}
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(void)Opc;
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assert((Opc == AArch64::STPXi || Opc == AArch64::STPDi ||
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Opc == AArch64::STRXui || Opc == AArch64::STRDui ||
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Opc == AArch64::LDPXi || Opc == AArch64::LDPDi ||
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Opc == AArch64::LDRXui || Opc == AArch64::LDRDui) &&
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"Unexpected callee-save save/restore opcode!");
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unsigned Scale;
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switch (Opc) {
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case AArch64::STPXi:
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case AArch64::STRXui:
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case AArch64::STPDi:
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case AArch64::STRDui:
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case AArch64::LDPXi:
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case AArch64::LDRXui:
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case AArch64::LDPDi:
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case AArch64::LDRDui:
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Scale = 8;
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break;
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default:
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llvm_unreachable("Unexpected callee-save save/restore opcode!");
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}
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unsigned OffsetIdx = MI.getNumExplicitOperands() - 1;
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assert(MI.getOperand(OffsetIdx - 1).getReg() == AArch64::SP &&
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@ -537,7 +542,7 @@ static void fixupCalleeSaveRestoreStackOffset(MachineInstr &MI,
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MachineOperand &OffsetOpnd = MI.getOperand(OffsetIdx);
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// All generated opcodes have scaled offsets.
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assert(LocalStackSize % 8 == 0);
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OffsetOpnd.setImm(OffsetOpnd.getImm() + LocalStackSize / 8);
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OffsetOpnd.setImm(OffsetOpnd.getImm() + LocalStackSize / Scale);
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}
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static void adaptForLdStOpt(MachineBasicBlock &MBB,
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@ -1203,7 +1208,7 @@ struct RegPairInfo {
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unsigned Reg2 = AArch64::NoRegister;
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int FrameIdx;
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int Offset;
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bool IsGPR;
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enum RegType { GPR, FPR64 } Type;
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RegPairInfo() = default;
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@ -1237,16 +1242,26 @@ static void computeCalleeSaveRegisterPairs(
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RegPairInfo RPI;
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RPI.Reg1 = CSI[i].getReg();
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assert(AArch64::GPR64RegClass.contains(RPI.Reg1) ||
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AArch64::FPR64RegClass.contains(RPI.Reg1));
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RPI.IsGPR = AArch64::GPR64RegClass.contains(RPI.Reg1);
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if (AArch64::GPR64RegClass.contains(RPI.Reg1))
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RPI.Type = RegPairInfo::GPR;
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else if (AArch64::FPR64RegClass.contains(RPI.Reg1))
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RPI.Type = RegPairInfo::FPR64;
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else
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llvm_unreachable("Unsupported register class.");
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// Add the next reg to the pair if it is in the same register class.
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if (i + 1 < Count) {
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unsigned NextReg = CSI[i + 1].getReg();
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if ((RPI.IsGPR && AArch64::GPR64RegClass.contains(NextReg)) ||
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(!RPI.IsGPR && AArch64::FPR64RegClass.contains(NextReg)))
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RPI.Reg2 = NextReg;
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switch (RPI.Type) {
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case RegPairInfo::GPR:
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if (AArch64::GPR64RegClass.contains(NextReg))
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RPI.Reg2 = NextReg;
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break;
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case RegPairInfo::FPR64:
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if (AArch64::FPR64RegClass.contains(NextReg))
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RPI.Reg2 = NextReg;
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break;
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}
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}
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// If either of the registers to be saved is the lr register, it means that
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@ -1343,10 +1358,19 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
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// Rationale: This sequence saves uop updates compared to a sequence of
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// pre-increment spills like stp xi,xj,[sp,#-16]!
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// Note: Similar rationale and sequence for restores in epilog.
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if (RPI.IsGPR)
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StrOpc = RPI.isPaired() ? AArch64::STPXi : AArch64::STRXui;
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else
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StrOpc = RPI.isPaired() ? AArch64::STPDi : AArch64::STRDui;
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unsigned Size, Align;
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switch (RPI.Type) {
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case RegPairInfo::GPR:
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StrOpc = RPI.isPaired() ? AArch64::STPXi : AArch64::STRXui;
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Size = 8;
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Align = 8;
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break;
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case RegPairInfo::FPR64:
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StrOpc = RPI.isPaired() ? AArch64::STPDi : AArch64::STRDui;
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Size = 8;
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Align = 8;
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break;
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}
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LLVM_DEBUG(dbgs() << "CSR spill: (" << printReg(Reg1, TRI);
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if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);
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dbgs() << ") -> fi#(" << RPI.FrameIdx;
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@ -1362,15 +1386,16 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
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MIB.addReg(Reg2, getPrologueDeath(MF, Reg2));
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MIB.addMemOperand(MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx + 1),
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MachineMemOperand::MOStore, 8, 8));
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MachineMemOperand::MOStore, Size, Align));
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}
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MIB.addReg(Reg1, getPrologueDeath(MF, Reg1))
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.addReg(AArch64::SP)
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.addImm(RPI.Offset) // [sp, #offset*8], where factor*8 is implicit
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.addImm(RPI.Offset) // [sp, #offset*scale],
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// where factor*scale is implicit
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.setMIFlag(MachineInstr::FrameSetup);
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MIB.addMemOperand(MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx),
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MachineMemOperand::MOStore, 8, 8));
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MachineMemOperand::MOStore, Size, Align));
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}
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return true;
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}
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@ -1404,10 +1429,19 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
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// ldp x22, x21, [sp, #0] // addImm(+0)
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// Note: see comment in spillCalleeSavedRegisters()
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unsigned LdrOpc;
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if (RPI.IsGPR)
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LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui;
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else
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LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui;
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unsigned Size, Align;
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switch (RPI.Type) {
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case RegPairInfo::GPR:
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LdrOpc = RPI.isPaired() ? AArch64::LDPXi : AArch64::LDRXui;
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Size = 8;
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Align = 8;
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break;
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case RegPairInfo::FPR64:
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LdrOpc = RPI.isPaired() ? AArch64::LDPDi : AArch64::LDRDui;
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Size = 8;
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Align = 8;
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break;
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}
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LLVM_DEBUG(dbgs() << "CSR restore: (" << printReg(Reg1, TRI);
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if (RPI.isPaired()) dbgs() << ", " << printReg(Reg2, TRI);
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dbgs() << ") -> fi#(" << RPI.FrameIdx;
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@ -1419,15 +1453,16 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters(
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MIB.addReg(Reg2, getDefRegState(true));
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MIB.addMemOperand(MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx + 1),
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MachineMemOperand::MOLoad, 8, 8));
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MachineMemOperand::MOLoad, Size, Align));
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}
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MIB.addReg(Reg1, getDefRegState(true))
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.addReg(AArch64::SP)
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.addImm(RPI.Offset) // [sp, #offset*8] where the factor*8 is implicit
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.addImm(RPI.Offset) // [sp, #offset*scale]
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// where factor*scale is implicit
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.setMIFlag(MachineInstr::FrameDestroy);
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MIB.addMemOperand(MF.getMachineMemOperand(
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MachinePointerInfo::getFixedStack(MF, RPI.FrameIdx),
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MachineMemOperand::MOLoad, 8, 8));
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MachineMemOperand::MOLoad, Size, Align));
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};
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if (ReverseCSRRestoreSeq)
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