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RenameIndependentSubregs: Fix handling of undef tied operands 

Ensure that, if updating a tied operand pair, to only update
that pair.

Differential Revision: https://reviews.llvm.org/D49052

llvm-svn: 336593
This commit is contained in:
Mark Searles 2018-07-09 20:07:03 +00:00
parent c1943e75c7
commit 7139dea6d9
2 changed files with 27 additions and 5 deletions
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14
llvm/lib/CodeGen/RenameIndependentSubregs.cpp
View File

@ -219,7 +219,8 @@ void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes,
if (!MO.isDef() && !MO.readsReg())
continue;
SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent());
auto *MI = MO.getParent();
SlotIndex Pos = LIS->getInstructionIndex(*MI);
Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
: Pos.getBaseIndex();
unsigned SubRegIdx = MO.getSubReg();
@ -245,11 +246,14 @@ void RenameIndependentSubregs::rewriteOperands(const IntEqClasses &Classes,
MO.setReg(VReg);
if (MO.isTied() && Reg != VReg) {
/// Undef use operands are not tracked in the equivalence class but need
/// to be update if they are tied.
MO.getParent()->substituteRegister(Reg, VReg, 0, TRI);
/// Undef use operands are not tracked in the equivalence class,
/// but need to be updated if they are tied; take care to only
/// update the tied operand.
unsigned OperandNo = MI->getOperandNo(&MO);
unsigned TiedIdx = MI->findTiedOperandIdx(OperandNo);
MI->getOperand(TiedIdx).setReg(VReg);
// substituteRegister breaks the iterator, so restart.
// above substitution breaks the iterator, so restart.
I = MRI->reg_nodbg_begin(Reg);
}
}

18
llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
View File

@ -2,6 +2,7 @@
--- |
define amdgpu_kernel void @test0() { ret void }
define amdgpu_kernel void @test1() { ret void }
define amdgpu_kernel void @test2() { ret void }
...
---
# In the test below we have two independent def+use pairs of subregister1 which
@ -67,3 +68,20 @@ body: |
S_NOP 0, implicit %0.sub2
...
# In this test, there are two pairs of tied operands
# within the inline asm statement:
# (1) %0.sub0 + %0.sub0 and (2) %0.sub1 + %0.sub1
# Check that renaming (2) does not inadvertently rename (1).
# CHECK-LABEL: name: test2
# CHECK: INLINEASM &"", 32, 327690, def undef %0.sub0, 327690, def dead %1.sub1, 2147483657, undef %0.sub0(tied-def 3), 2147549193, %1.sub1(tied-def 5)
name: test2
body: |
bb.0:
undef %0.sub0:vreg_64 = IMPLICIT_DEF
bb.1:
undef %0.sub1:vreg_64 = V_ALIGNBIT_B32 %0.sub0:vreg_64, %0.sub0:vreg_64, 16, implicit $exec
INLINEASM &"", 32, 327690, def undef %0.sub0:vreg_64, 327690, def %0.sub1:vreg_64, 2147483657, undef %0.sub0:vreg_64(tied-def 3), 2147549193, %0.sub1:vreg_64(tied-def 5)
S_BRANCH %bb.1
...