forked from OSchip/llvm-project
[RISCV] add support for zbkx subextension in MC layer.
This patch adds support for zbkx extension from K extension(v1.0.0) in MC layer.
Instructions with same functionality and same encoding is defined in the bitmanip extension.
It defines {Xperm8, Xperm4} as instruction aliases for xperm.* in Zbp extension. When Zbkx is enabled while Zbp is not, xperm.h will not be available. When Zbkx and Zbp are both enabled, the instructions will be decoded in Zbp format.
[[ https://reviews.llvm.org/D94999 | D94999 ]] this is the patch that introduces xperm.* instructions.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D117889
This commit is contained in:
SForeKeeper
parent
b7f69b8d46
commit
70f83f3084
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@ -58,6 +58,7 @@ static const RISCVSupportedExtension SupportedExtensions[] = {
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{"zbkb", RISCVExtensionVersion{1, 0}},
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{"zbkc", RISCVExtensionVersion{1, 0}},
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{"zbkx", RISCVExtensionVersion{1, 0}},
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{"zknd", RISCVExtensionVersion{1, 0}},
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{"zkne", RISCVExtensionVersion{1, 0}},
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{"zknh", RISCVExtensionVersion{1, 0}},
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@ -770,8 +771,8 @@ static const char *ImpliedExtsZvl256b[] = {"zvl128b"};
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static const char *ImpliedExtsZvl128b[] = {"zvl64b"};
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static const char *ImpliedExtsZvl64b[] = {"zvl32b"};
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static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
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static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zkne", "zknd", "zknh"};
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static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zksed", "zksh"};
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static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"};
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static const char *ImpliedExtsZks[] = {"zbkb", "zbkc", "zbkx", "zksed", "zksh"};
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struct ImpliedExtsEntry {
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StringLiteral Name;
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@ -150,6 +150,19 @@ def HasStdExtZbkb : Predicate<"Subtarget->hasStdExtZbkb()">,
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AssemblerPredicate<(all_of FeatureStdExtZbkb),
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"'Zbkb' (Bitmanip instructions for Cryptography)">;
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def FeatureStdExtZbkx
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: SubtargetFeature<"zbkx", "HasStdExtZbkx", "true",
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"'Zbkx' (Crossbar permutation instructions)">;
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def HasStdExtZbkx : Predicate<"Subtarget->hasStdExtZbkx()">,
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AssemblerPredicate<(all_of FeatureStdExtZbkx),
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"'Zbkx' (Crossbar permutation instructions)">;
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def HasStdExtZbpOrZbkx
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: Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkx()">,
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AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkx),
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"'Zbp' (Permutation 'Zb' Instructions) or "
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"'Zbkx' (Crossbar permutation instructions)">;
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def HasStdExtZbpOrZbkb
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: Predicate<"Subtarget->hasStdExtZbp() || Subtarget->hasStdExtZbkb()">,
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AssemblerPredicate<(any_of FeatureStdExtZbp, FeatureStdExtZbkb),
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@ -233,6 +246,7 @@ def FeatureStdExtZkn
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"'Zkn' (NIST Algorithm Suite)",
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[FeatureStdExtZbkb,
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FeatureStdExtZbkc,
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FeatureStdExtZbkx,
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FeatureStdExtZkne,
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FeatureStdExtZknd,
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FeatureStdExtZknh]>;
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@ -242,6 +256,7 @@ def FeatureStdExtZks
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"'Zks' (ShangMi Algorithm Suite)",
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[FeatureStdExtZbkb,
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FeatureStdExtZbkc,
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FeatureStdExtZbkx,
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FeatureStdExtZksed,
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FeatureStdExtZksh]>;
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@ -27,6 +27,7 @@
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// versions:
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// Zbkb - 1.0
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// Zbkc - 1.0
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// Zbkx - 1.0
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//
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//===----------------------------------------------------------------------===//
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@ -359,9 +360,12 @@ def GORC : ALU_rr<0b0010100, 0b101, "gorc">, Sched<[]>;
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def GREV : ALU_rr<0b0110100, 0b101, "grev">, Sched<[]>;
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} // Predicates = [HasStdExtZbp]
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let Predicates = [HasStdExtZbpOrZbkx] in {
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def XPERMN : ALU_rr<0b0010100, 0b010, "xperm4">, Sched<[]>;
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def XPERMB : ALU_rr<0b0010100, 0b100, "xperm8">, Sched<[]>;
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} // Predicates = [HasStdExtZbpOrZbkx]
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let Predicates = [HasStdExtZbp] in {
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def XPERMN : ALU_rr<0b0010100, 0b010, "xperm.n">, Sched<[]>;
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def XPERMB : ALU_rr<0b0010100, 0b100, "xperm.b">, Sched<[]>;
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def XPERMH : ALU_rr<0b0010100, 0b110, "xperm.h">, Sched<[]>;
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} // Predicates = [HasStdExtZbp]
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@ -768,6 +772,13 @@ def : InstAlias<"gorcw $rd, $rs1, $shamt",
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(GORCIW GPR:$rd, GPR:$rs1, uimm5:$shamt), 0>;
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} // Predicates = [HasStdExtZbp, IsRV64]
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// Zbp is unratified and that it would likely adopt the already ratified Zbkx names.
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// Thus current Zbp instructions are defined as aliases for Zbkx instructions.
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let Predicates = [HasStdExtZbp] in {
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def : InstAlias<"xperm.b $rd, $rs1, $rs2", (XPERMB GPR:$rd, GPR:$rs1, GPR:$rs2)>;
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def : InstAlias<"xperm.n $rd, $rs1, $rs2", (XPERMN GPR:$rd, GPR:$rs1, GPR:$rs2)>;
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} // Predicates = [HasStdExtZbp]
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let Predicates = [HasStdExtZbs] in {
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def : InstAlias<"bset $rd, $rs1, $shamt",
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(BSETI GPR:$rd, GPR:$rs1, uimmlog2xlen:$shamt), 0>;
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@ -17,10 +17,10 @@ def RocketModel : SchedMachineModel {
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let LoadLatency = 3;
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let MispredictPenalty = 3;
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let CompleteModel = false;
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let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZknd,
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HasStdExtZkne, HasStdExtZknh, HasStdExtZksed,
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HasStdExtZksh, HasStdExtZkr, HasVInstructions,
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HasVInstructionsI64];
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let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
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HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
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HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
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HasVInstructions, HasVInstructionsI64];
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}
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//===----------------------------------------------------------------------===//
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@ -15,9 +15,10 @@ def SiFive7Model : SchedMachineModel {
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let LoadLatency = 3;
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let MispredictPenalty = 3;
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let CompleteModel = 0;
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let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZknd,
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HasStdExtZkne, HasStdExtZknh, HasStdExtZksed,
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HasStdExtZksh, HasStdExtZkr, HasVInstructions];
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let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
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HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
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HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
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HasVInstructions];
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}
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// The SiFive7 microarchitecture has two pipelines: A and B.
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@ -85,6 +85,7 @@ private:
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bool HasStdExtZfh = false;
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bool HasStdExtZbkb = false;
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bool HasStdExtZbkc = false;
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bool HasStdExtZbkx = false;
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bool HasStdExtZknd = false;
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bool HasStdExtZkne = false;
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bool HasStdExtZknh = false;
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@ -170,6 +171,7 @@ public:
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bool hasStdExtZfh() const { return HasStdExtZfh; }
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bool hasStdExtZbkb() const { return HasStdExtZbkb; }
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bool hasStdExtZbkc() const { return HasStdExtZbkc; }
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bool hasStdExtZbkx() const { return HasStdExtZbkx; }
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bool hasStdExtZknd() const { return HasStdExtZknd; }
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bool hasStdExtZkne() const { return HasStdExtZkne; }
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bool hasStdExtZknh() const { return HasStdExtZknh; }
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@ -21,6 +21,7 @@
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; RUN: llc -mtriple=riscv32 -mattr=+zbb,+zfh,+v,+f %s -o - | FileCheck --check-prefix=RV32COMBINED %s
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; RUN: llc -mtriple=riscv32 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV32ZBKB %s
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; RUN: llc -mtriple=riscv32 -mattr=+zbkc %s -o - | FileCheck --check-prefix=RV32ZBKC %s
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; RUN: llc -mtriple=riscv32 -mattr=+zbkx %s -o - | FileCheck --check-prefix=RV32ZBKX %s
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; RUN: llc -mtriple=riscv32 -mattr=+zknd %s -o - | FileCheck --check-prefix=RV32ZKND %s
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; RUN: llc -mtriple=riscv32 -mattr=+zkne %s -o - | FileCheck --check-prefix=RV32ZKNE %s
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; RUN: llc -mtriple=riscv32 -mattr=+zknh %s -o - | FileCheck --check-prefix=RV32ZKNH %s
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@ -52,6 +53,7 @@
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; RUN: llc -mtriple=riscv64 -mattr=+zbb,+zfh,+v,+f %s -o - | FileCheck --check-prefix=RV64COMBINED %s
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; RUN: llc -mtriple=riscv64 -mattr=+zbkb %s -o - | FileCheck --check-prefix=RV64ZBKB %s
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; RUN: llc -mtriple=riscv64 -mattr=+zbkc %s -o - | FileCheck --check-prefix=RV64ZBKC %s
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; RUN: llc -mtriple=riscv64 -mattr=+zbkx %s -o - | FileCheck --check-prefix=RV64ZBKX %s
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; RUN: llc -mtriple=riscv64 -mattr=+zknd %s -o - | FileCheck --check-prefix=RV64ZKND %s
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; RUN: llc -mtriple=riscv64 -mattr=+zkne %s -o - | FileCheck --check-prefix=RV64ZKNE %s
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; RUN: llc -mtriple=riscv64 -mattr=+zknh %s -o - | FileCheck --check-prefix=RV64ZKNH %s
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@ -84,16 +86,17 @@
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; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_d2p0_v1p0_zfh1p0_zfhmin1p0_zbb1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
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; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"
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; RV32ZBKC: .attribute 5, "rv32i2p0_zbkc1p0"
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; RV32ZBKX: .attribute 5, "rv32i2p0_zbkx1p0"
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; RV32ZKND: .attribute 5, "rv32i2p0_zknd1p0"
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; RV32ZKNE: .attribute 5, "rv32i2p0_zkne1p0"
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; RV32ZKNH: .attribute 5, "rv32i2p0_zknh1p0"
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; RV32ZKSED: .attribute 5, "rv32i2p0_zksed1p0"
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; RV32ZKSH: .attribute 5, "rv32i2p0_zksh1p0"
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; RV32ZKR: .attribute 5, "rv32i2p0_zkr1p0"
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; RV32ZKN: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
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; RV32ZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zks1p0_zksed1p0_zksh1p0"
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; RV32ZKN: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
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; RV32ZKS: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
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; RV32ZKT: .attribute 5, "rv32i2p0_zkt1p0"
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; RV32ZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
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; RV32ZK: .attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
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; RV64M: .attribute 5, "rv64i2p0_m2p0"
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; RV64A: .attribute 5, "rv64i2p0_a2p0"
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@ -116,16 +119,17 @@
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; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_d2p0_v1p0_zfh1p0_zfhmin1p0_zbb1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
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; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"
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; RV64ZBKC: .attribute 5, "rv64i2p0_zbkc1p0"
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; RV64ZBKX: .attribute 5, "rv64i2p0_zbkx1p0"
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; RV64ZKND: .attribute 5, "rv64i2p0_zknd1p0"
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; RV64ZKNE: .attribute 5, "rv64i2p0_zkne1p0"
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; RV64ZKNH: .attribute 5, "rv64i2p0_zknh1p0"
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; RV64ZKSED: .attribute 5, "rv64i2p0_zksed1p0"
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; RV64ZKSH: .attribute 5, "rv64i2p0_zksh1p0"
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; RV64ZKR: .attribute 5, "rv64i2p0_zkr1p0"
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; RV64ZKN: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
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; RV64ZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zks1p0_zksed1p0_zksh1p0"
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; RV64ZKN: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
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; RV64ZKS: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
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; RV64ZKT: .attribute 5, "rv64i2p0_zkt1p0"
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; RV64ZK: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
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; RV64ZK: .attribute 5, "rv64i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
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define i32 @addi(i32 %a) {
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%1 = add i32 %a, 1
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@ -131,6 +131,9 @@
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.attribute arch, "rv32i_zbkc1p0"
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# CHECK: attribute 5, "rv32i2p0_zbkc1p0"
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.attribute arch, "rv32i_zbkx1p0"
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# CHECK: attribute 5, "rv32i2p0_zbkx1p0"
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.attribute arch, "rv32i_zknd1p0"
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# CHECK: attribute 5, "rv32i2p0_zknd1p0"
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@ -150,13 +153,13 @@
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# CHECK: attribute 5, "rv32i2p0_zkr1p0"
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.attribute arch, "rv32i_zkn1p0"
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# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
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# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0"
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.attribute arch, "rv32i_zks1p0"
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# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zks1p0_zksed1p0_zksh1p0"
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# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zks1p0_zksed1p0_zksh1p0"
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.attribute arch, "rv32i_zkt1p0"
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# CHECK: attribute 5, "rv32i2p0_zkt1p0"
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.attribute arch, "rv32i_zk1p0"
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# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
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# CHECK: attribute 5, "rv32i2p0_zbkb1p0_zbkc1p0_zbkx1p0_zk1p0_zkn1p0_zknd1p0_zkne1p0_zknh1p0_zkr1p0_zkt1p0"
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@ -0,0 +1,9 @@
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# RUN: not llvm-mc -triple riscv32 -mattr=+zbkx < %s 2>&1 | FileCheck %s
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# Too few operands
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xperm8 t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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# Too few operands
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xperm4 t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
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# Undefined Zbp instruction in Zbkx
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xperm.h t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: 'Zbp' (Permutation 'B' Instructions)
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@ -0,0 +1,17 @@
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# RUN: llvm-mc %s -triple=riscv32 -mattr=+zbkx -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc %s -triple=riscv64 -mattr=+zbkx -show-encoding \
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# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=zbkx < %s \
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# RUN: | llvm-objdump --mattr=+zbkx -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=zbkx < %s \
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# RUN: | llvm-objdump --mattr=+zbkx -d -r - \
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# RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s
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# CHECK-ASM-AND-OBJ: xperm8 t0, t1, t2
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# CHECK-ASM: encoding: [0xb3,0x42,0x73,0x28]
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xperm8 t0, t1, t2
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# CHECK-ASM-AND-OBJ: xperm4 t0, t1, t2
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# CHECK-ASM: encoding: [0xb3,0x22,0x73,0x28]
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xperm4 t0, t1, t2
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