forked from OSchip/llvm-project
Convert INSERT_SUBREG to COPY in TwoAddressInstructionPass.
INSERT_SUBREG will now only appear in SSA machine instructions. Fix the handling of partial redefs in ProcessImplicitDefs. This is now relevant since partial redef COPY instructions appear. llvm-svn: 107726
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@ -265,7 +265,7 @@ bool MultipleDefsBySameMI(const MachineInstr &MI, unsigned MOIdx) {
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if (MO.getReg() == Reg && MO.isDef()) {
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assert(MI.getOperand(MOIdx).getSubReg() != MO.getSubReg() &&
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MI.getOperand(MOIdx).getSubReg() &&
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MO.getSubReg());
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(MO.getSubReg() || MO.isImplicit()));
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return true;
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}
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}
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@ -117,10 +117,24 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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}
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}
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// Eliminate %reg1032:sub<def> = COPY undef.
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if (MI->isCopy() && MI->getOperand(0).getSubReg()) {
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MachineOperand &MO = MI->getOperand(1);
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if (ImpDefRegs.count(MO.getReg())) {
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if (MO.isKill()) {
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LiveVariables::VarInfo& vi = lv_->getVarInfo(MO.getReg());
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vi.removeKill(MI);
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}
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MI->eraseFromParent();
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Changed = true;
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continue;
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}
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}
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bool ChangedToImpDef = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand& MO = MI->getOperand(i);
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if (!MO.isReg() || !MO.isUse() || MO.isUndef())
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if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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@ -145,6 +159,12 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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Changed = true;
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MO.setIsUndef();
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// This is a partial register redef of an implicit def.
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// Make sure the whole register is defined by the instruction.
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if (MO.isDef()) {
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MI->addRegisterDefined(Reg);
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continue;
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}
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if (MO.isKill() || MI->isRegTiedToDefOperand(i)) {
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// Make sure other uses of
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for (unsigned j = i+1; j != e; ++j) {
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@ -1218,6 +1218,19 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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DEBUG(dbgs() << "\t\trewrite to:\t" << *mi);
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}
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// Rewrite INSERT_SUBREG as COPY now that we no longer need SSA form.
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if (mi->isInsertSubreg()) {
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// From %reg = INSERT_SUBREG %reg, %subreg, subidx
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// To %reg:subidx = COPY %subreg
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unsigned SubIdx = mi->getOperand(3).getImm();
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mi->RemoveOperand(3);
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assert(mi->getOperand(0).getSubReg() == 0 && "Unexpected subreg idx");
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mi->getOperand(0).setSubReg(SubIdx);
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mi->RemoveOperand(1);
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mi->setDesc(TII->get(TargetOpcode::COPY));
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DEBUG(dbgs() << "\t\tconvert to:\t" << *mi);
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}
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// Clear TiedOperands here instead of at the top of the loop
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// since most instructions do not have tied operands.
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TiedOperands.clear();
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