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[RISCV] Prefer vmslt.vx v0, v8, zero over vmsle.vi v0, v8, -1. 

At least when starting from a vmslt.vx intrinsic or ISD::SETLT. We
don't handle the case where the user used vmsle.vx intrinsic with -1.
This commit is contained in:
Craig Topper 2022-01-27 11:47:53 -08:00
parent 024a1fab5c
commit 70e1cc6792
8 changed files with 23 additions and 21 deletions
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14
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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@ -3836,7 +3836,7 @@ multiclass VPatConversionVF_WF <string intrinsic, string instruction> {
}
multiclass VPatCompare_VI<string intrinsic, string inst,
ImmLeaf ImmType = simm5_plus1> {
ImmLeaf ImmType> {
foreach vti = AllIntegerVectors in {
defvar Intr = !cast<Intrinsic>(intrinsic);
defvar Pseudo = !cast<Instruction>(inst#"_VI_"#vti.LMul.MX);
@ -4657,13 +4657,15 @@ defm : VPatBinarySwappedM_VV<"int_riscv_vmsgt", "PseudoVMSLT", AllIntegerVectors
defm : VPatBinarySwappedM_VV<"int_riscv_vmsgeu", "PseudoVMSLEU", AllIntegerVectors>;
defm : VPatBinarySwappedM_VV<"int_riscv_vmsge", "PseudoVMSLE", AllIntegerVectors>;
// Match vmslt(u).vx intrinsics to vmsle(u).vi if the scalar is -15 to 16. This
// avoids the user needing to know that there is no vmslt(u).vi instruction.
// Similar for vmsge(u).vx intrinsics using vmslt(u).vi.
defm : VPatCompare_VI<"int_riscv_vmslt", "PseudoVMSLE">;
// Match vmslt(u).vx intrinsics to vmsle(u).vi if the scalar is -15 to 16 and
// non-zero. Zero can be .vx with x0. This avoids the user needing to know that
// there is no vmslt(u).vi instruction. Similar for vmsge(u).vx intrinsics
// using vmslt(u).vi.
defm : VPatCompare_VI<"int_riscv_vmslt", "PseudoVMSLE", simm5_plus1_nonzero>;
defm : VPatCompare_VI<"int_riscv_vmsltu", "PseudoVMSLEU", simm5_plus1_nonzero>;
defm : VPatCompare_VI<"int_riscv_vmsge", "PseudoVMSGT">;
// We need to handle 0 for vmsge.vi using vmslt.vi because there is no vmsge.vx.
defm : VPatCompare_VI<"int_riscv_vmsge", "PseudoVMSGT", simm5_plus1>;
defm : VPatCompare_VI<"int_riscv_vmsgeu", "PseudoVMSGTU", simm5_plus1_nonzero>;
//===----------------------------------------------------------------------===//

2
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
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@ -539,7 +539,7 @@ defm : VPatIntegerSetCCSDNode_VV_VX_VI<SETNE, "PseudoVMSNE">;
defm : VPatIntegerSetCCSDNode_VV_VX<SETLT, "PseudoVMSLT">;
defm : VPatIntegerSetCCSDNode_VV_VX<SETULT, "PseudoVMSLTU">;
defm : VPatIntegerSetCCSDNode_VIPlus1<SETLT, "PseudoVMSLE",
SplatPat_simm5_plus1>;
SplatPat_simm5_plus1_nonzero>;
defm : VPatIntegerSetCCSDNode_VIPlus1<SETULT, "PseudoVMSLEU",
SplatPat_simm5_plus1_nonzero>;

2
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
View File

@ -832,7 +832,7 @@ foreach vti = AllIntegerVectors in {
defm : VPatIntegerSetCCVL_VI_Swappable<vti, "PseudoVMSGTU", SETUGT, SETULT>;
defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLE", SETLT,
SplatPat_simm5_plus1>;
SplatPat_simm5_plus1_nonzero>;
defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSLEU", SETULT,
SplatPat_simm5_plus1_nonzero>;
defm : VPatIntegerSetCCVL_VIPlus1<vti, "PseudoVMSGT", SETGE,

2
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-setcc.ll
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@ -587,7 +587,7 @@ define void @setlt_vi_v128i8(<128 x i8>* %x, <128 x i1>* %z) {
; CHECK-NEXT: li a2, 128
; CHECK-NEXT: vsetvli zero, a2, e8, m8, ta, mu
; CHECK-NEXT: vle8.v v8, (a0)
; CHECK-NEXT: vmsle.vi v16, v8, -1
; CHECK-NEXT: vmslt.vx v16, v8, zero
; CHECK-NEXT: vsm.v v16, (a1)
; CHECK-NEXT: ret
%a = load <128 x i8>, <128 x i8>* %x

8
llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv32.ll
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@ -676,7 +676,7 @@ define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i8_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vmslt.vx v0, v8, zero
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@ -1418,7 +1418,7 @@ define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i16_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vmslt.vx v0, v8, zero
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@ -2146,7 +2146,7 @@ define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i32_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vmslt.vx v0, v8, zero
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@ -2989,7 +2989,7 @@ define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i64_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vmslt.vx v0, v8, zero
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer

8
llvm/test/CodeGen/RISCV/rvv/setcc-integer-rv64.ll
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@ -690,7 +690,7 @@ define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i8_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, mu
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vmslt.vx v0, v8, zero
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> undef, i8 0, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> undef, <vscale x 8 x i32> zeroinitializer
@ -1418,7 +1418,7 @@ define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i16_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vmslt.vx v0, v8, zero
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> undef, i16 0, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
@ -2146,7 +2146,7 @@ define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i32_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vmslt.vx v0, v8, zero
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> undef, i32 0, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> undef, <vscale x 8 x i32> zeroinitializer
@ -2874,7 +2874,7 @@ define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
; CHECK-LABEL: icmp_slt_vi_nxv8i64_2:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vmslt.vx v0, v8, zero
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> undef, i64 0, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> undef, <vscale x 8 x i32> zeroinitializer

4
llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll
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@ -2085,7 +2085,7 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i16_i16(<vscale x 2 x i1>
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v10, v8, -1, v0.t
; CHECK-NEXT: vmslt.vx v10, v8, zero, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
@ -2103,7 +2103,7 @@ define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i16_i16(<vscale x 4 x i16> %0,
; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vmslt.vx v0, v8, zero
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16.i16(

4
llvm/test/CodeGen/RISCV/rvv/vmslt-rv64.ll
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@ -2049,7 +2049,7 @@ define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i16_i16(<vscale x 2 x i1>
; CHECK-NEXT: vmv1r.v v10, v0
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmsle.vi v10, v8, -1, v0.t
; CHECK-NEXT: vmslt.vx v10, v8, zero, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: ret
entry:
@ -2067,7 +2067,7 @@ define <vscale x 4 x i1> @intrinsic_vmslt_vi_nxv4i16_i16(<vscale x 4 x i16> %0,
; CHECK-LABEL: intrinsic_vmslt_vi_nxv4i16_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vmslt.vx v0, v8, zero
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.nxv4i16.i16(