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Add missing test cases for ARM VLD3 (single 3-element structure to all lanes) 

instructions.

llvm-svn: 155453
This commit is contained in:
Kevin Enderby 2012-04-24 17:45:56 +00:00
parent 2a9c509c7e
commit 70be447e5c
2 changed files with 38 additions and 0 deletions
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19
llvm/test/MC/Disassembler/ARM/neon.txt
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@ -1734,6 +1734,25 @@
0xcf 0x1a 0xe0 0xf4
# CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0]
# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]
0x0f 0x0e 0xa4 0xf4
# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]!
0x0d 0x0e 0xa4 0xf4
# CHECK: vld3.8 {d0[], d2[], d4[]}, [r4], r5
0x25 0x0e 0xa4 0xf4
# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4]
0x6f 0x0e 0xa4 0xf4
# CHECK: vld3.16 {d0[], d1[], d2[]}, [r4]!
0x4d 0x0e 0xa4 0xf4
# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4], r5
0x65 0x0e 0xa4 0xf4
# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4]
0x8f 0x0e 0xa4 0xf4
# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4]!
0x8d 0x0e 0xa4 0xf4
# CHECK: vld3.32 {d0[], d2[], d4[]}, [r4], r5
0xa5 0x0e 0xa4 0xf4
0x3f 0x03 0xe0 0xf4
# CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
0x4f 0x07 0xe0 0xf4

19
llvm/test/MC/Disassembler/ARM/neont2.txt
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@ -1475,6 +1475,25 @@
0xe0 0xf9 0xcf 0x1a
# CHECK: vld3.32 {d17[1], d19[1], d21[1]}, [r0]
0xa4 0xf9 0x0f 0x0e
# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]
0xa4 0xf9 0x0d 0x0e
# CHECK: vld3.8 {d0[], d1[], d2[]}, [r4]!
0xa4 0xf9 0x25 0x0e
# CHECK: vld3.8 {d0[], d2[], d4[]}, [r4], r5
0xa4 0xf9 0x6f 0x0e
# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4]
0xa4 0xf9 0x4d 0x0e
# CHECK: vld3.16 {d0[], d1[], d2[]}, [r4]!
0xa4 0xf9 0x65 0x0e
# CHECK: vld3.16 {d0[], d2[], d4[]}, [r4], r5
0xa4 0xf9 0x8f 0x0e
# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4]
0xa4 0xf9 0x8d 0x0e
# CHECK: vld3.32 {d0[], d1[], d2[]}, [r4]!
0xa4 0xf9 0xa5 0x0e
# CHECK: vld3.32 {d0[], d2[], d4[]}, [r4], r5
0xe0 0xf9 0x3f 0x03
# CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
0xe0 0xf9 0x4f 0x07