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[CSKY] Fix the btsti16 instruction missing in generic processor 

Normally, generic processor does not have any SubtargetFeature. And it
can just generate most basic instructions which have no Predicates to
guard.

But it needs to enbale predicate for the btsti16 instruction as one of the most basic instructions.
Or the generic processor can't finish codegen process. So Add FeatureBTST16 SubtargetFeature to generic ProcessorModel.
This commit is contained in:
Zi Xuan Wu (Zeson) 2022-07-27 17:16:01 +08:00 committed by Zi Xuan Wu
parent dc84eeb62b
commit 70b8b738c5
9 changed files with 975 additions and 1194 deletions
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4
llvm/lib/Target/CSKY/CSKY.td
View File

@ -373,7 +373,9 @@ include "CSKYInstrInfo.td"
// CSKY processors supported.
//===----------------------------------------------------------------------===//
def : ProcessorModel<"generic", NoSchedModel, []>;
// btsti16 is one of most basic instructions should be enable
// even in generic processor to avoid failure codegen.
def : ProcessorModel<"generic", NoSchedModel, [FeatureBTST16]>;
// CK801 series
class CK801<string n, SchedMachineModel m, list<SubtargetFeature> f,

1500
llvm/test/CodeGen/CSKY/atomic-rmw.ll
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File diff suppressed because it is too large Load Diff

6
llvm/test/CodeGen/CSKY/base-i.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+e2 -mattr=+2e3 < %s -mtriple=csky | FileCheck %s
; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+btst16 < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC
define i32 @addRR(i32 %x, i32 %y) {
; CHECK-LABEL: addRR:
@ -279,9 +279,9 @@ define i64 @SUB_LONG(i64 %x, i64 %y) {
; CHECK-NEXT: setc32
; CHECK-NEXT: subc32 a0, a2, a0
; CHECK-NEXT: mvcv16 a2
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: mvcv16 a2
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: subc32 a1, a3, a1
; CHECK-NEXT: rts16
;

124
llvm/test/CodeGen/CSKY/br.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3 | FileCheck %s
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+btst16 | FileCheck %s --check-prefix=GENERIC
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC
;EQ
define i32 @brRR_eq(i32 %x, i32 %y) {
@ -1390,15 +1390,15 @@ define i64 @brRR_i64_ugt(i64 %x, i64 %y) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 8)
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a1, (sp, 12)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB35_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -1473,9 +1473,9 @@ define i64 @brRI_i64_ugt(i64 %x) {
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: movi16 a1, 0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB36_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -1580,9 +1580,9 @@ define i64 @brRR_i64_uge(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a2, a0
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB38_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -1650,9 +1650,9 @@ define i64 @brRI_i64_uge(i64 %x) {
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: movi16 a1, 0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB39_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -1717,15 +1717,15 @@ define i64 @brRR_i64_ult(i64 %x, i64 %y) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 8)
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a1, (sp, 12)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB40_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -1796,7 +1796,7 @@ define i64 @brRI_i64_ult(i64 %x) {
; CHECK-NEXT: cmpnei16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB41_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -1861,9 +1861,9 @@ define i64 @brRR_i64_ule(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a0, a2
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB42_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -1927,7 +1927,7 @@ define i64 @brRI_i64_ule(i64 %x) {
; CHECK-NEXT: cmpnei16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB43_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -2034,12 +2034,12 @@ define i64 @brRR_i64_sgt(i64 %x, i64 %y) {
; CHECK-NEXT: cmplt16 a1, a3
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB45_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -2106,12 +2106,12 @@ define i64 @brRI_i64_sgt(i64 %x) {
; CHECK-NEXT: cmphsi16 a0, 11
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB46_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -2179,12 +2179,12 @@ define i64 @brR0_i64_sgt(i64 %x) {
; CHECK-NEXT: cmpnei16 a0, 0
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB47_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -2252,12 +2252,12 @@ define i64 @brRR_i64_sge(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a2, a0
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB48_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -2329,12 +2329,12 @@ define i64 @brRI_i64_sge(i64 %x) {
; CHECK-NEXT: cmphsi16 a0, 10
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB49_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -2443,12 +2443,12 @@ define i64 @brRR_i64_slt(i64 %x, i64 %y) {
; CHECK-NEXT: cmplt16 a3, a1
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB51_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -2516,12 +2516,12 @@ define i64 @brRI_i64_slt(i64 %x) {
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: st16.w a1, (sp, 4)
; CHECK-NEXT: ld16.w a1, (sp, 8)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB52_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -2640,12 +2640,12 @@ define i64 @brRR_i64_sle(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a0, a2
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB54_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -2718,12 +2718,12 @@ define i64 @brRI_i64_sle(i64 %x) {
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: st16.w a1, (sp, 4)
; CHECK-NEXT: ld16.w a1, (sp, 8)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB55_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -2793,15 +2793,15 @@ define i64 @brR0_i64_sle(i64 %x) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 8)
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a1, (sp, 12)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: bt32 .LBB56_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -5500,7 +5500,7 @@ define i1 @brRI_i1_eq(i1 %x) {
; CHECK-LABEL: brRI_i1_eq:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bf32 .LBB117_2
; CHECK-NEXT: # %bb.1: # %label2
; CHECK-NEXT: movi16 a0, 0
@ -5539,7 +5539,7 @@ define i1 @brR0_i1_eq(i1 %x) {
; CHECK-LABEL: brR0_i1_eq:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bf32 .LBB118_2
; CHECK-NEXT: # %bb.1: # %label2
; CHECK-NEXT: movi16 a0, 0
@ -5864,7 +5864,7 @@ define i1 @brRI_i1_uge(i1 %x) {
; CHECK-LABEL: brRI_i1_uge:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB126_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -5948,7 +5948,7 @@ define i1 @brRI_i1_ult(i1 %x) {
; CHECK-LABEL: brRI_i1_ult:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB128_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -6033,7 +6033,7 @@ define i1 @brRI_i1_ule(i1 %x) {
; CHECK-LABEL: brRI_i1_ule:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB130_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -6074,7 +6074,7 @@ define i1 @brR0_i1_ule(i1 %x) {
; CHECK-LABEL: brR0_i1_ule:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB131_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -6160,7 +6160,7 @@ define i1 @brRI_i1_sgt(i1 %x) {
; CHECK-LABEL: brRI_i1_sgt:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB133_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -6200,7 +6200,7 @@ define i1 @brR0_i1_sgt(i1 %x) {
; CHECK-LABEL: brR0_i1_sgt:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movi16 a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB134_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -6285,7 +6285,7 @@ define i1 @brRI_i1_sge(i1 %x) {
; CHECK-LABEL: brRI_i1_sge:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB136_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -6326,7 +6326,7 @@ define i1 @brR0_i1_sge(i1 %x) {
; CHECK-LABEL: brR0_i1_sge:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi32 a0, a0, 1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB137_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -6537,7 +6537,7 @@ define i1 @brRI_i1_sle(i1 %x) {
; CHECK-LABEL: brRI_i1_sle:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB142_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1
@ -6577,7 +6577,7 @@ define i1 @brR0_i1_sle(i1 %x) {
; CHECK-LABEL: brR0_i1_sle:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB143_2
; CHECK-NEXT: # %bb.1: # %label1
; CHECK-NEXT: movi16 a0, 1

54
llvm/test/CodeGen/CSKY/cmp-i.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3 | FileCheck %s
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+btst16 | FileCheck %s --check-prefix=GENERIC
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC
;eq
define i1 @icmpRR_eq(i32 %x, i32 %y) {
@ -687,7 +687,7 @@ define i1 @ICMP_LONG_ugt(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a0, a2
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: addi16 sp, sp, 8
@ -1016,13 +1016,13 @@ define i1 @ICMP_LONG_uge(i64 %x, i64 %y) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 8)
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a0, (sp, 12)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 16
; CHECK-NEXT: rts16
@ -1345,7 +1345,7 @@ define i1 @ICMP_LONG_ult(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a2, a0
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: addi16 sp, sp, 8
@ -1658,13 +1658,13 @@ define i1 @ICMP_LONG_ule(i64 %x, i64 %y) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 8)
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a0, (sp, 12)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 16
; CHECK-NEXT: rts16
@ -1718,7 +1718,7 @@ define i1 @ICMP_LONG_I_ule(i64 %x) {
; CHECK-NEXT: mvcv16 a1
; CHECK-NEXT: movi16 a0, 0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 8
; CHECK-NEXT: rts16
@ -2007,10 +2007,10 @@ define i1 @ICMP_LONG_sgt(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a0, a2
; CHECK-NEXT: mvcv16 a1
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 12
; CHECK-NEXT: rts16
@ -2061,10 +2061,10 @@ define i1 @ICMP_LONG_I_sgt(i64 %x) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 4)
; CHECK-NEXT: ld16.w a0, (sp, 8)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movf32 a0, a2
; CHECK-NEXT: addi16 sp, sp, 12
; CHECK-NEXT: rts16
@ -2340,10 +2340,10 @@ define i1 @ICMP_LONG_sge(i64 %x, i64 %y) {
; CHECK-NEXT: cmplt16 a3, a1
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 12
; CHECK-NEXT: rts16
@ -2389,13 +2389,13 @@ define i1 @ICMP_LONG_I_sge(i64 %x) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 8)
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a0, (sp, 12)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 16
; CHECK-NEXT: rts16
@ -2671,10 +2671,10 @@ define i1 @ICMP_LONG_slt(i64 %x, i64 %y) {
; CHECK-NEXT: cmphs16 a2, a0
; CHECK-NEXT: mvcv16 a1
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 12
; CHECK-NEXT: rts16
@ -2724,10 +2724,10 @@ define i1 @ICMP_LONG_I_slt(i64 %x) {
; CHECK-NEXT: cmpnei16 a0, 0
; CHECK-NEXT: mvcv16 a1
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 12
; CHECK-NEXT: rts16
@ -2998,10 +2998,10 @@ define i1 @ICMP_LONG_sle(i64 %x, i64 %y) {
; CHECK-NEXT: cmplt16 a1, a3
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 12
; CHECK-NEXT: rts16
@ -3046,10 +3046,10 @@ define i1 @ICMP_LONG_I_sle(i64 %x) {
; CHECK-NEXT: cmphsi16 a0, 2
; CHECK-NEXT: mvcv16 a1
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 sp, sp, 12
; CHECK-NEXT: rts16

96
llvm/test/CodeGen/CSKY/fpu/br-d.ll
View File

@ -139,7 +139,7 @@ define i32 @brRR_one(double %x, double %y) {
; CHECK-DF-NEXT: fcmpned vr1, vr0
; CHECK-DF-NEXT: mvcv16 a1
; CHECK-DF-NEXT: or16 a0, a1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB3_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -155,7 +155,7 @@ define i32 @brRR_one(double %x, double %y) {
; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0
; CHECK-DF2-NEXT: mvcv16 a1
; CHECK-DF2-NEXT: or16 a0, a1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB3_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -184,7 +184,7 @@ define i32 @brRI_one(double %x) {
; CHECK-DF-NEXT: fcmpned vr0, vr1
; CHECK-DF-NEXT: mvcv16 a1
; CHECK-DF-NEXT: or16 a0, a1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB4_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -206,7 +206,7 @@ define i32 @brRI_one(double %x) {
; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
; CHECK-DF2-NEXT: mvcv16 a1
; CHECK-DF2-NEXT: or16 a0, a1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB4_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -240,7 +240,7 @@ define i32 @brR0_one(double %x) {
; CHECK-DF-NEXT: fcmpned vr0, vr1
; CHECK-DF-NEXT: mvcv16 a1
; CHECK-DF-NEXT: or16 a0, a1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB5_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -262,7 +262,7 @@ define i32 @brR0_one(double %x) {
; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
; CHECK-DF2-NEXT: mvcv16 a1
; CHECK-DF2-NEXT: or16 a0, a1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB5_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -797,7 +797,7 @@ define i32 @brRR_ogt(double %x, double %y) {
; CHECK-DF-NEXT: fcmpltd vr0, vr1
; CHECK-DF-NEXT: mvc32 a0
; CHECK-DF-NEXT: xori32 a0, a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB18_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -811,7 +811,7 @@ define i32 @brRR_ogt(double %x, double %y) {
; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1
; CHECK-DF2-NEXT: mvc32 a0
; CHECK-DF2-NEXT: xori32 a0, a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB18_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -838,7 +838,7 @@ define i32 @brRI_ogt(double %x) {
; CHECK-DF-NEXT: fcmpltd vr1, vr0
; CHECK-DF-NEXT: mvc32 a0
; CHECK-DF-NEXT: xori32 a0, a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB19_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -858,7 +858,7 @@ define i32 @brRI_ogt(double %x) {
; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0
; CHECK-DF2-NEXT: mvc32 a0
; CHECK-DF2-NEXT: xori32 a0, a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB19_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -890,7 +890,7 @@ define i32 @brR0_ogt(double %x) {
; CHECK-DF-NEXT: fcmpltd vr1, vr0
; CHECK-DF-NEXT: mvc32 a0
; CHECK-DF-NEXT: xori32 a0, a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB20_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -910,7 +910,7 @@ define i32 @brR0_ogt(double %x) {
; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0
; CHECK-DF2-NEXT: mvc32 a0
; CHECK-DF2-NEXT: xori32 a0, a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB20_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -941,7 +941,7 @@ define i32 @brRR_oge(double %x, double %y) {
; CHECK-DF-NEXT: fcmphsd vr1, vr0
; CHECK-DF-NEXT: mvc32 a0
; CHECK-DF-NEXT: xori32 a0, a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB21_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -955,7 +955,7 @@ define i32 @brRR_oge(double %x, double %y) {
; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0
; CHECK-DF2-NEXT: mvc32 a0
; CHECK-DF2-NEXT: xori32 a0, a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB21_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -982,7 +982,7 @@ define i32 @brRI_oge(double %x) {
; CHECK-DF-NEXT: fcmphsd vr0, vr1
; CHECK-DF-NEXT: mvc32 a0
; CHECK-DF-NEXT: xori32 a0, a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB22_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -1002,7 +1002,7 @@ define i32 @brRI_oge(double %x) {
; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1
; CHECK-DF2-NEXT: mvc32 a0
; CHECK-DF2-NEXT: xori32 a0, a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB22_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -1034,7 +1034,7 @@ define i32 @brR0_oge(double %x) {
; CHECK-DF-NEXT: fcmphsd vr0, vr1
; CHECK-DF-NEXT: mvc32 a0
; CHECK-DF-NEXT: xori32 a0, a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB23_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -1054,7 +1054,7 @@ define i32 @brR0_oge(double %x) {
; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1
; CHECK-DF2-NEXT: mvc32 a0
; CHECK-DF2-NEXT: xori32 a0, a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB23_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -1085,7 +1085,7 @@ define i32 @brRR_olt(double %x, double %y) {
; CHECK-DF-NEXT: fcmpltd vr1, vr0
; CHECK-DF-NEXT: mvc32 a0
; CHECK-DF-NEXT: xori32 a0, a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB24_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -1099,7 +1099,7 @@ define i32 @brRR_olt(double %x, double %y) {
; CHECK-DF2-NEXT: fcmplt.64 vr1, vr0
; CHECK-DF2-NEXT: mvc32 a0
; CHECK-DF2-NEXT: xori32 a0, a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB24_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -1126,7 +1126,7 @@ define i32 @brRI_olt(double %x) {
; CHECK-DF-NEXT: fcmpltd vr0, vr1
; CHECK-DF-NEXT: mvc32 a0
; CHECK-DF-NEXT: xori32 a0, a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB25_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -1146,7 +1146,7 @@ define i32 @brRI_olt(double %x) {
; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1
; CHECK-DF2-NEXT: mvc32 a0
; CHECK-DF2-NEXT: xori32 a0, a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB25_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -1178,7 +1178,7 @@ define i32 @brR0_olt(double %x) {
; CHECK-DF-NEXT: fcmpltd vr0, vr1
; CHECK-DF-NEXT: mvc32 a0
; CHECK-DF-NEXT: xori32 a0, a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB26_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -1198,7 +1198,7 @@ define i32 @brR0_olt(double %x) {
; CHECK-DF2-NEXT: fcmplt.64 vr0, vr1
; CHECK-DF2-NEXT: mvc32 a0
; CHECK-DF2-NEXT: xori32 a0, a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB26_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -1229,7 +1229,7 @@ define i32 @brRR_ole(double %x, double %y) {
; CHECK-DF-NEXT: fcmphsd vr0, vr1
; CHECK-DF-NEXT: mvc32 a0
; CHECK-DF-NEXT: xori32 a0, a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB27_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -1243,7 +1243,7 @@ define i32 @brRR_ole(double %x, double %y) {
; CHECK-DF2-NEXT: fcmphs.64 vr0, vr1
; CHECK-DF2-NEXT: mvc32 a0
; CHECK-DF2-NEXT: xori32 a0, a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB27_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -1270,7 +1270,7 @@ define i32 @brRI_ole(double %x) {
; CHECK-DF-NEXT: fcmphsd vr1, vr0
; CHECK-DF-NEXT: mvc32 a0
; CHECK-DF-NEXT: xori32 a0, a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB28_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -1290,7 +1290,7 @@ define i32 @brRI_ole(double %x) {
; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0
; CHECK-DF2-NEXT: mvc32 a0
; CHECK-DF2-NEXT: xori32 a0, a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB28_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -1322,7 +1322,7 @@ define i32 @brR0_ole(double %x) {
; CHECK-DF-NEXT: fcmphsd vr1, vr0
; CHECK-DF-NEXT: mvc32 a0
; CHECK-DF-NEXT: xori32 a0, a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB29_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -1342,7 +1342,7 @@ define i32 @brR0_ole(double %x) {
; CHECK-DF2-NEXT: fcmphs.64 vr1, vr0
; CHECK-DF2-NEXT: mvc32 a0
; CHECK-DF2-NEXT: xori32 a0, a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB29_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -1371,7 +1371,7 @@ define i32 @brRR_false(double %x, double %y) {
; CHECK-DF-LABEL: brRR_false:
; CHECK-DF: # %bb.0: # %entry
; CHECK-DF-NEXT: movi16 a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB30_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -1383,7 +1383,7 @@ define i32 @brRR_false(double %x, double %y) {
; CHECK-DF2-LABEL: brRR_false:
; CHECK-DF2: # %bb.0: # %entry
; CHECK-DF2-NEXT: movi16 a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB30_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -1406,7 +1406,7 @@ define i32 @brRI_false(double %x) {
; CHECK-DF-LABEL: brRI_false:
; CHECK-DF: # %bb.0: # %entry
; CHECK-DF-NEXT: movi16 a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB31_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -1418,7 +1418,7 @@ define i32 @brRI_false(double %x) {
; CHECK-DF2-LABEL: brRI_false:
; CHECK-DF2: # %bb.0: # %entry
; CHECK-DF2-NEXT: movi16 a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB31_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -1441,7 +1441,7 @@ define i32 @brR0_false(double %x) {
; CHECK-DF-LABEL: brR0_false:
; CHECK-DF: # %bb.0: # %entry
; CHECK-DF-NEXT: movi16 a0, 1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB32_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -1453,7 +1453,7 @@ define i32 @brR0_false(double %x) {
; CHECK-DF2-LABEL: brR0_false:
; CHECK-DF2: # %bb.0: # %entry
; CHECK-DF2-NEXT: movi16 a0, 1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB32_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -1583,7 +1583,7 @@ define i32 @brRR_ueq(double %x, double %y) {
; CHECK-DF-NEXT: fcmpned vr1, vr0
; CHECK-DF-NEXT: mvc32 a1
; CHECK-DF-NEXT: and16 a0, a1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bf32 .LBB36_2
; CHECK-DF-NEXT: # %bb.1: # %label2
; CHECK-DF-NEXT: movi16 a0, 0
@ -1599,7 +1599,7 @@ define i32 @brRR_ueq(double %x, double %y) {
; CHECK-DF2-NEXT: fcmpne.64 vr1, vr0
; CHECK-DF2-NEXT: mvc32 a1
; CHECK-DF2-NEXT: and16 a0, a1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bf32 .LBB36_2
; CHECK-DF2-NEXT: # %bb.1: # %label2
; CHECK-DF2-NEXT: movi16 a0, 0
@ -1628,7 +1628,7 @@ define i32 @brRI_ueq(double %x) {
; CHECK-DF-NEXT: fcmpned vr0, vr1
; CHECK-DF-NEXT: mvc32 a1
; CHECK-DF-NEXT: and16 a0, a1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bf32 .LBB37_2
; CHECK-DF-NEXT: # %bb.1: # %label2
; CHECK-DF-NEXT: movi16 a0, 0
@ -1650,7 +1650,7 @@ define i32 @brRI_ueq(double %x) {
; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
; CHECK-DF2-NEXT: mvc32 a1
; CHECK-DF2-NEXT: and16 a0, a1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bf32 .LBB37_2
; CHECK-DF2-NEXT: # %bb.1: # %label2
; CHECK-DF2-NEXT: movi16 a0, 0
@ -1684,7 +1684,7 @@ define i32 @brR0_ueq(double %x) {
; CHECK-DF-NEXT: fcmpned vr0, vr1
; CHECK-DF-NEXT: mvc32 a1
; CHECK-DF-NEXT: and16 a0, a1
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bf32 .LBB38_2
; CHECK-DF-NEXT: # %bb.1: # %label2
; CHECK-DF-NEXT: movi16 a0, 0
@ -1706,7 +1706,7 @@ define i32 @brR0_ueq(double %x) {
; CHECK-DF2-NEXT: fcmpne.64 vr0, vr1
; CHECK-DF2-NEXT: mvc32 a1
; CHECK-DF2-NEXT: and16 a0, a1
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bf32 .LBB38_2
; CHECK-DF2-NEXT: # %bb.1: # %label2
; CHECK-DF2-NEXT: movi16 a0, 0
@ -1961,7 +1961,7 @@ define i32 @brRR_true(double %x, double %y) {
; CHECK-DF-LABEL: brRR_true:
; CHECK-DF: # %bb.0: # %entry
; CHECK-DF-NEXT: movi16 a0, 0
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB45_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -1973,7 +1973,7 @@ define i32 @brRR_true(double %x, double %y) {
; CHECK-DF2-LABEL: brRR_true:
; CHECK-DF2: # %bb.0: # %entry
; CHECK-DF2-NEXT: movi16 a0, 0
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB45_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -1996,7 +1996,7 @@ define i32 @brRI_true(double %x) {
; CHECK-DF-LABEL: brRI_true:
; CHECK-DF: # %bb.0: # %entry
; CHECK-DF-NEXT: movi16 a0, 0
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB46_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -2008,7 +2008,7 @@ define i32 @brRI_true(double %x) {
; CHECK-DF2-LABEL: brRI_true:
; CHECK-DF2: # %bb.0: # %entry
; CHECK-DF2-NEXT: movi16 a0, 0
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB46_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1
@ -2031,7 +2031,7 @@ define i32 @brR0_true(double %x) {
; CHECK-DF-LABEL: brR0_true:
; CHECK-DF: # %bb.0: # %entry
; CHECK-DF-NEXT: movi16 a0, 0
; CHECK-DF-NEXT: btsti32 a0, 0
; CHECK-DF-NEXT: btsti16 a0, 0
; CHECK-DF-NEXT: bt32 .LBB47_2
; CHECK-DF-NEXT: # %bb.1: # %label1
; CHECK-DF-NEXT: movi16 a0, 1
@ -2043,7 +2043,7 @@ define i32 @brR0_true(double %x) {
; CHECK-DF2-LABEL: brR0_true:
; CHECK-DF2: # %bb.0: # %entry
; CHECK-DF2-NEXT: movi16 a0, 0
; CHECK-DF2-NEXT: btsti32 a0, 0
; CHECK-DF2-NEXT: btsti16 a0, 0
; CHECK-DF2-NEXT: bt32 .LBB47_2
; CHECK-DF2-NEXT: # %bb.1: # %label1
; CHECK-DF2-NEXT: movi16 a0, 1

96
llvm/test/CodeGen/CSKY/fpu/br-f.ll
View File

@ -113,7 +113,7 @@ define i32 @brRR_one(float %x, float %y) {
; CHECK-SF-NEXT: fcmpnes vr1, vr0
; CHECK-SF-NEXT: mvcv16 a1
; CHECK-SF-NEXT: or16 a0, a1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB3_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -129,7 +129,7 @@ define i32 @brRR_one(float %x, float %y) {
; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0
; CHECK-SF2-NEXT: mvcv16 a1
; CHECK-SF2-NEXT: or16 a0, a1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB3_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -157,7 +157,7 @@ define i32 @brRI_one(float %x) {
; CHECK-SF-NEXT: fcmpuos vr0, vr0
; CHECK-SF-NEXT: mvc32 a1
; CHECK-SF-NEXT: or16 a0, a1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB4_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -175,7 +175,7 @@ define i32 @brRI_one(float %x) {
; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
; CHECK-SF2-NEXT: mvc32 a1
; CHECK-SF2-NEXT: or16 a0, a1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB4_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -201,7 +201,7 @@ define i32 @brR0_one(float %x) {
; CHECK-SF-NEXT: fcmpznes vr0
; CHECK-SF-NEXT: mvcv16 a1
; CHECK-SF-NEXT: or16 a0, a1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB5_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -217,7 +217,7 @@ define i32 @brR0_one(float %x) {
; CHECK-SF2-NEXT: fcmpnez.32 vr0
; CHECK-SF2-NEXT: mvcv16 a1
; CHECK-SF2-NEXT: or16 a0, a1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB5_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -646,7 +646,7 @@ define i32 @brRR_ogt(float %x, float %y) {
; CHECK-SF-NEXT: fcmplts vr0, vr1
; CHECK-SF-NEXT: mvc32 a0
; CHECK-SF-NEXT: xori32 a0, a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB18_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -660,7 +660,7 @@ define i32 @brRR_ogt(float %x, float %y) {
; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1
; CHECK-SF2-NEXT: mvc32 a0
; CHECK-SF2-NEXT: xori32 a0, a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB18_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -686,7 +686,7 @@ define i32 @brRI_ogt(float %x) {
; CHECK-SF-NEXT: fcmplts vr1, vr0
; CHECK-SF-NEXT: mvc32 a0
; CHECK-SF-NEXT: xori32 a0, a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB19_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -702,7 +702,7 @@ define i32 @brRI_ogt(float %x) {
; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0
; CHECK-SF2-NEXT: mvc32 a0
; CHECK-SF2-NEXT: xori32 a0, a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB19_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -726,7 +726,7 @@ define i32 @brR0_ogt(float %x) {
; CHECK-SF-NEXT: fcmpzlss vr0
; CHECK-SF-NEXT: mvcv16 a0
; CHECK-SF-NEXT: xori32 a0, a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB20_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -740,7 +740,7 @@ define i32 @brR0_ogt(float %x) {
; CHECK-SF2-NEXT: fcmphz.32 vr0
; CHECK-SF2-NEXT: mvc32 a0
; CHECK-SF2-NEXT: xori32 a0, a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB20_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -765,7 +765,7 @@ define i32 @brRR_oge(float %x, float %y) {
; CHECK-SF-NEXT: fcmphss vr1, vr0
; CHECK-SF-NEXT: mvc32 a0
; CHECK-SF-NEXT: xori32 a0, a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB21_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -779,7 +779,7 @@ define i32 @brRR_oge(float %x, float %y) {
; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0
; CHECK-SF2-NEXT: mvc32 a0
; CHECK-SF2-NEXT: xori32 a0, a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB21_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -805,7 +805,7 @@ define i32 @brRI_oge(float %x) {
; CHECK-SF-NEXT: fcmphss vr0, vr1
; CHECK-SF-NEXT: mvc32 a0
; CHECK-SF-NEXT: xori32 a0, a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB22_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -821,7 +821,7 @@ define i32 @brRI_oge(float %x) {
; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1
; CHECK-SF2-NEXT: mvc32 a0
; CHECK-SF2-NEXT: xori32 a0, a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB22_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -845,7 +845,7 @@ define i32 @brR0_oge(float %x) {
; CHECK-SF-NEXT: fcmpzhss vr0
; CHECK-SF-NEXT: mvc32 a0
; CHECK-SF-NEXT: xori32 a0, a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB23_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -859,7 +859,7 @@ define i32 @brR0_oge(float %x) {
; CHECK-SF2-NEXT: fcmphsz.32 vr0
; CHECK-SF2-NEXT: mvc32 a0
; CHECK-SF2-NEXT: xori32 a0, a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB23_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -884,7 +884,7 @@ define i32 @brRR_olt(float %x, float %y) {
; CHECK-SF-NEXT: fcmplts vr1, vr0
; CHECK-SF-NEXT: mvc32 a0
; CHECK-SF-NEXT: xori32 a0, a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB24_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -898,7 +898,7 @@ define i32 @brRR_olt(float %x, float %y) {
; CHECK-SF2-NEXT: fcmplt.32 vr1, vr0
; CHECK-SF2-NEXT: mvc32 a0
; CHECK-SF2-NEXT: xori32 a0, a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB24_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -924,7 +924,7 @@ define i32 @brRI_olt(float %x) {
; CHECK-SF-NEXT: fcmplts vr0, vr1
; CHECK-SF-NEXT: mvc32 a0
; CHECK-SF-NEXT: xori32 a0, a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB25_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -940,7 +940,7 @@ define i32 @brRI_olt(float %x) {
; CHECK-SF2-NEXT: fcmplt.32 vr0, vr1
; CHECK-SF2-NEXT: mvc32 a0
; CHECK-SF2-NEXT: xori32 a0, a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB25_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -964,7 +964,7 @@ define i32 @brR0_olt(float %x) {
; CHECK-SF-NEXT: fcmpzhss vr0
; CHECK-SF-NEXT: mvcv16 a0
; CHECK-SF-NEXT: xori32 a0, a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB26_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -978,7 +978,7 @@ define i32 @brR0_olt(float %x) {
; CHECK-SF2-NEXT: fcmpltz.32 vr0
; CHECK-SF2-NEXT: mvc32 a0
; CHECK-SF2-NEXT: xori32 a0, a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB26_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -1003,7 +1003,7 @@ define i32 @brRR_ole(float %x, float %y) {
; CHECK-SF-NEXT: fcmphss vr0, vr1
; CHECK-SF-NEXT: mvc32 a0
; CHECK-SF-NEXT: xori32 a0, a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB27_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -1017,7 +1017,7 @@ define i32 @brRR_ole(float %x, float %y) {
; CHECK-SF2-NEXT: fcmphs.32 vr0, vr1
; CHECK-SF2-NEXT: mvc32 a0
; CHECK-SF2-NEXT: xori32 a0, a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB27_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -1043,7 +1043,7 @@ define i32 @brRI_ole(float %x) {
; CHECK-SF-NEXT: fcmphss vr1, vr0
; CHECK-SF-NEXT: mvc32 a0
; CHECK-SF-NEXT: xori32 a0, a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB28_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -1059,7 +1059,7 @@ define i32 @brRI_ole(float %x) {
; CHECK-SF2-NEXT: fcmphs.32 vr1, vr0
; CHECK-SF2-NEXT: mvc32 a0
; CHECK-SF2-NEXT: xori32 a0, a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB28_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -1083,7 +1083,7 @@ define i32 @brR0_ole(float %x) {
; CHECK-SF-NEXT: fcmpzlss vr0
; CHECK-SF-NEXT: mvc32 a0
; CHECK-SF-NEXT: xori32 a0, a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB29_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -1097,7 +1097,7 @@ define i32 @brR0_ole(float %x) {
; CHECK-SF2-NEXT: fcmplsz.32 vr0
; CHECK-SF2-NEXT: mvc32 a0
; CHECK-SF2-NEXT: xori32 a0, a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB29_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -1120,7 +1120,7 @@ define i32 @brRR_false(float %x, float %y) {
; CHECK-SF-LABEL: brRR_false:
; CHECK-SF: # %bb.0: # %entry
; CHECK-SF-NEXT: movi16 a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB30_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -1132,7 +1132,7 @@ define i32 @brRR_false(float %x, float %y) {
; CHECK-SF2-LABEL: brRR_false:
; CHECK-SF2: # %bb.0: # %entry
; CHECK-SF2-NEXT: movi16 a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB30_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -1154,7 +1154,7 @@ define i32 @brRI_false(float %x) {
; CHECK-SF-LABEL: brRI_false:
; CHECK-SF: # %bb.0: # %entry
; CHECK-SF-NEXT: movi16 a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB31_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -1166,7 +1166,7 @@ define i32 @brRI_false(float %x) {
; CHECK-SF2-LABEL: brRI_false:
; CHECK-SF2: # %bb.0: # %entry
; CHECK-SF2-NEXT: movi16 a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB31_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -1188,7 +1188,7 @@ define i32 @brR0_false(float %x) {
; CHECK-SF-LABEL: brR0_false:
; CHECK-SF: # %bb.0: # %entry
; CHECK-SF-NEXT: movi16 a0, 1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB32_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -1200,7 +1200,7 @@ define i32 @brR0_false(float %x) {
; CHECK-SF2-LABEL: brR0_false:
; CHECK-SF2: # %bb.0: # %entry
; CHECK-SF2-NEXT: movi16 a0, 1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB32_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -1326,7 +1326,7 @@ define i32 @brRR_ueq(float %x, float %y) {
; CHECK-SF-NEXT: fcmpnes vr1, vr0
; CHECK-SF-NEXT: mvc32 a1
; CHECK-SF-NEXT: and16 a0, a1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bf32 .LBB36_2
; CHECK-SF-NEXT: # %bb.1: # %label2
; CHECK-SF-NEXT: movi16 a0, 0
@ -1342,7 +1342,7 @@ define i32 @brRR_ueq(float %x, float %y) {
; CHECK-SF2-NEXT: fcmpne.32 vr1, vr0
; CHECK-SF2-NEXT: mvc32 a1
; CHECK-SF2-NEXT: and16 a0, a1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bf32 .LBB36_2
; CHECK-SF2-NEXT: # %bb.1: # %label2
; CHECK-SF2-NEXT: movi16 a0, 0
@ -1370,7 +1370,7 @@ define i32 @brRI_ueq(float %x) {
; CHECK-SF-NEXT: fcmpuos vr0, vr0
; CHECK-SF-NEXT: mvcv16 a1
; CHECK-SF-NEXT: and16 a0, a1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bf32 .LBB37_2
; CHECK-SF-NEXT: # %bb.1: # %label2
; CHECK-SF-NEXT: movi16 a0, 0
@ -1388,7 +1388,7 @@ define i32 @brRI_ueq(float %x) {
; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
; CHECK-SF2-NEXT: mvcv16 a1
; CHECK-SF2-NEXT: and16 a0, a1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bf32 .LBB37_2
; CHECK-SF2-NEXT: # %bb.1: # %label2
; CHECK-SF2-NEXT: movi16 a0, 0
@ -1414,7 +1414,7 @@ define i32 @brR0_ueq(float %x) {
; CHECK-SF-NEXT: fcmpznes vr0
; CHECK-SF-NEXT: mvc32 a1
; CHECK-SF-NEXT: and16 a0, a1
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bf32 .LBB38_2
; CHECK-SF-NEXT: # %bb.1: # %label2
; CHECK-SF-NEXT: movi16 a0, 0
@ -1432,7 +1432,7 @@ define i32 @brR0_ueq(float %x) {
; CHECK-SF2-NEXT: fcmpuo.32 vr0, vr0
; CHECK-SF2-NEXT: mvcv16 a1
; CHECK-SF2-NEXT: and16 a0, a1
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bf32 .LBB38_2
; CHECK-SF2-NEXT: # %bb.1: # %label2
; CHECK-SF2-NEXT: movi16 a0, 0
@ -1653,7 +1653,7 @@ define i32 @brRR_true(float %x, float %y) {
; CHECK-SF-LABEL: brRR_true:
; CHECK-SF: # %bb.0: # %entry
; CHECK-SF-NEXT: movi16 a0, 0
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB45_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -1665,7 +1665,7 @@ define i32 @brRR_true(float %x, float %y) {
; CHECK-SF2-LABEL: brRR_true:
; CHECK-SF2: # %bb.0: # %entry
; CHECK-SF2-NEXT: movi16 a0, 0
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB45_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -1687,7 +1687,7 @@ define i32 @brRI_true(float %x) {
; CHECK-SF-LABEL: brRI_true:
; CHECK-SF: # %bb.0: # %entry
; CHECK-SF-NEXT: movi16 a0, 0
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB46_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -1699,7 +1699,7 @@ define i32 @brRI_true(float %x) {
; CHECK-SF2-LABEL: brRI_true:
; CHECK-SF2: # %bb.0: # %entry
; CHECK-SF2-NEXT: movi16 a0, 0
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB46_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1
@ -1721,7 +1721,7 @@ define i32 @brR0_true(float %x) {
; CHECK-SF-LABEL: brR0_true:
; CHECK-SF: # %bb.0: # %entry
; CHECK-SF-NEXT: movi16 a0, 0
; CHECK-SF-NEXT: btsti32 a0, 0
; CHECK-SF-NEXT: btsti16 a0, 0
; CHECK-SF-NEXT: bt32 .LBB47_2
; CHECK-SF-NEXT: # %bb.1: # %label1
; CHECK-SF-NEXT: movi16 a0, 1
@ -1733,7 +1733,7 @@ define i32 @brR0_true(float %x) {
; CHECK-SF2-LABEL: brR0_true:
; CHECK-SF2: # %bb.0: # %entry
; CHECK-SF2-NEXT: movi16 a0, 0
; CHECK-SF2-NEXT: btsti32 a0, 0
; CHECK-SF2-NEXT: btsti16 a0, 0
; CHECK-SF2-NEXT: bt32 .LBB47_2
; CHECK-SF2-NEXT: # %bb.1: # %label1
; CHECK-SF2-NEXT: movi16 a0, 1

11
llvm/test/CodeGen/CSKY/fpu/select.ll
View File

@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3,+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3,+hard-float,+fpuv3_sf,+fpuv3_df -float-abi=hard | FileCheck %s --check-prefix=CHECK-DF3
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+btst16,+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s --check-prefix=GENERIC
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+hard-float,+fpuv2_sf,+fpuv2_df -float-abi=hard | FileCheck %s --check-prefix=GENERIC
define float @selectRR_eq_float(i1 %x, float %n, float %m) {
; CHECK-LABEL: selectRR_eq_float:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB0_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: fmovs vr1, vr0
@ -16,7 +16,7 @@ define float @selectRR_eq_float(i1 %x, float %n, float %m) {
;
; CHECK-DF3-LABEL: selectRR_eq_float:
; CHECK-DF3: # %bb.0: # %entry
; CHECK-DF3-NEXT: btsti32 a0, 0
; CHECK-DF3-NEXT: btsti16 a0, 0
; CHECK-DF3-NEXT: fsel.32 vr0, vr1, vr0
; CHECK-DF3-NEXT: rts16
;
@ -41,7 +41,7 @@ entry:
define double @selectRR_eq_double(i1 %x, double %n, double %m) {
; CHECK-LABEL: selectRR_eq_double:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: bt32 .LBB1_2
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: fmovd vr1, vr0
@ -51,7 +51,7 @@ define double @selectRR_eq_double(i1 %x, double %n, double %m) {
;
; CHECK-DF3-LABEL: selectRR_eq_double:
; CHECK-DF3: # %bb.0: # %entry
; CHECK-DF3-NEXT: btsti32 a0, 0
; CHECK-DF3-NEXT: btsti16 a0, 0
; CHECK-DF3-NEXT: fsel.64 vr0, vr1, vr0
; CHECK-DF3-NEXT: rts16
;
@ -72,4 +72,3 @@ entry:
%ret = select i1 %x, double %m, double %n
ret double %ret
}

278
llvm/test/CodeGen/CSKY/select.ll
View File

@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+2e3 | FileCheck %s
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -mattr=+btst16 | FileCheck %s --check-prefix=GENERIC
; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC
define i32 @selectRR_eq_i32(i32 %x, i32 %y, i32 %n, i32 %m) {
; CHECK-LABEL: selectRR_eq_i32:
@ -109,7 +109,7 @@ entry:
define i32 @selectC_eq_i32(i1 %c, i32 %n, i32 %m) {
; CHECK-LABEL: selectC_eq_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -301,7 +301,7 @@ define i64 @selectC_eq_i64(i1 %c, i64 %n, i64 %m) {
; CHECK-LABEL: selectC_eq_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld32.w t0, (sp, 0)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a3
; CHECK-NEXT: movt32 a2, t0
; CHECK-NEXT: mov16 a0, a1
@ -487,7 +487,7 @@ entry:
define i16 @selectC_eq_i16(i1 %c, i16 %n, i16 %m) {
; CHECK-LABEL: selectC_eq_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -618,7 +618,7 @@ entry:
define i8 @selectC_eq_i8(i1 %c, i8 %n, i8 %m) {
; CHECK-LABEL: selectC_eq_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -646,7 +646,7 @@ define i1 @selectRR_eq_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
; CHECK-LABEL: selectRR_eq_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor16 a0, a1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a3, a2
; CHECK-NEXT: mov16 a0, a3
; CHECK-NEXT: rts16
@ -674,7 +674,7 @@ entry:
define i1 @selectRI_eq_i1(i1 %x, i1 %n, i1 %m) {
; CHECK-LABEL: selectRI_eq_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a2, a1
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
@ -701,7 +701,7 @@ entry:
define i1 @selectRX_eq_i1(i1 %x, i1 %n, i1 %m) {
; CHECK-LABEL: selectRX_eq_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -728,7 +728,7 @@ entry:
define i1 @selectC_eq_i1(i1 %c, i1 %n, i1 %m) {
; CHECK-LABEL: selectC_eq_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -865,7 +865,7 @@ entry:
define i32 @selectC_ne_i32(i1 %c, i32 %n, i32 %m) {
; CHECK-LABEL: selectC_ne_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -1063,7 +1063,7 @@ define i64 @selectC_ne_i64(i1 %c, i64 %n, i64 %m) {
; CHECK-LABEL: selectC_ne_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld32.w t0, (sp, 0)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a3
; CHECK-NEXT: movt32 a2, t0
; CHECK-NEXT: mov16 a0, a1
@ -1255,7 +1255,7 @@ entry:
define i16 @selectC_ne_i16(i1 %c, i16 %n, i16 %m) {
; CHECK-LABEL: selectC_ne_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -1392,7 +1392,7 @@ entry:
define i8 @selectC_ne_i8(i1 %c, i8 %n, i8 %m) {
; CHECK-LABEL: selectC_ne_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -1420,7 +1420,7 @@ define i1 @selectRR_ne_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
; CHECK-LABEL: selectRR_ne_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xor16 a0, a1
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a2, a3
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
@ -1448,7 +1448,7 @@ entry:
define i1 @selectRI_ne_i1(i1 %x, i1 %n, i1 %m) {
; CHECK-LABEL: selectRI_ne_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -1475,7 +1475,7 @@ entry:
define i1 @selectRX_ne_i1(i1 %x, i1 %n, i1 %m) {
; CHECK-LABEL: selectRX_ne_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a2, a1
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
@ -1502,7 +1502,7 @@ entry:
define i1 @selectC_ne_i1(i1 %c, i1 %n, i1 %m) {
; CHECK-LABEL: selectC_ne_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -1635,7 +1635,7 @@ entry:
define i32 @selectC_ugt_i32(i1 %c, i32 %n, i32 %m) {
; CHECK-LABEL: selectC_ugt_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -1672,11 +1672,11 @@ define i64 @selectRR_ugt_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
; CHECK-NEXT: cmphs16 a0, a2
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: addi16 a2, sp, 8
; CHECK-NEXT: addi16 a0, sp, 16
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, a0
; CHECK-NEXT: ld16.w a0, (a2, 0)
; CHECK-NEXT: ld16.w a1, (a2, 4)
@ -1740,7 +1740,7 @@ define i64 @selectRI_ugt_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: cmpnei16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -1812,7 +1812,7 @@ define i64 @selectRX_ugt_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: cmpnei16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -1883,7 +1883,7 @@ define i64 @selectC_ugt_i64(i1 %c, i64 %n, i64 %m) {
; CHECK-LABEL: selectC_ugt_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld32.w t0, (sp, 0)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a3
; CHECK-NEXT: movt32 a2, t0
; CHECK-NEXT: mov16 a0, a1
@ -2072,7 +2072,7 @@ entry:
define i16 @selectC_ugt_i16(i1 %c, i16 %n, i16 %m) {
; CHECK-LABEL: selectC_ugt_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -2206,7 +2206,7 @@ entry:
define i8 @selectC_ugt_i8(i1 %c, i8 %n, i8 %m) {
; CHECK-LABEL: selectC_ugt_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -2233,9 +2233,9 @@ entry:
define i1 @selectRR_ugt_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
; CHECK-LABEL: selectRR_ugt_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a3, a2
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, a3
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
@ -2271,7 +2271,7 @@ entry:
define i1 @selectRI_ugt_i1(i1 %x, i1 %n, i1 %m) {
; CHECK-LABEL: selectRI_ugt_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -2318,7 +2318,7 @@ entry:
define i1 @selectC_ugt_i1(i1 %c, i1 %n, i1 %m) {
; CHECK-LABEL: selectC_ugt_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -2453,7 +2453,7 @@ entry:
define i32 @selectC_uge_i32(i1 %c, i32 %n, i32 %m) {
; CHECK-LABEL: selectC_uge_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -2492,17 +2492,17 @@ define i64 @selectRR_uge_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 8)
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a1, (sp, 12)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: addi16 a2, sp, 16
; CHECK-NEXT: addi16 a0, sp, 24
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, a0
; CHECK-NEXT: ld16.w a0, (a2, 0)
; CHECK-NEXT: ld16.w a1, (a2, 4)
@ -2573,7 +2573,7 @@ define i64 @selectRI_uge_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: cmpnei16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -2645,7 +2645,7 @@ define i64 @selectRX_uge_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: cmpnei16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -2716,7 +2716,7 @@ define i64 @selectC_uge_i64(i1 %c, i64 %n, i64 %m) {
; CHECK-LABEL: selectC_uge_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld32.w t0, (sp, 0)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a3
; CHECK-NEXT: movt32 a2, t0
; CHECK-NEXT: mov16 a0, a1
@ -2907,7 +2907,7 @@ entry:
define i16 @selectC_uge_i16(i1 %c, i16 %n, i16 %m) {
; CHECK-LABEL: selectC_uge_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -3043,7 +3043,7 @@ entry:
define i8 @selectC_uge_i8(i1 %c, i8 %n, i8 %m) {
; CHECK-LABEL: selectC_uge_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -3070,10 +3070,10 @@ entry:
define i1 @selectRR_uge_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
; CHECK-LABEL: selectRR_uge_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mov16 a0, a3
; CHECK-NEXT: movt32 a0, a2
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a0, a3
; CHECK-NEXT: rts16
;
@ -3124,7 +3124,7 @@ entry:
define i1 @selectRX_uge_i1(i1 %x, i1 %n, i1 %m) {
; CHECK-LABEL: selectRX_uge_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -3151,7 +3151,7 @@ entry:
define i1 @selectC_uge_i1(i1 %c, i1 %n, i1 %m) {
; CHECK-LABEL: selectC_uge_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -3282,7 +3282,7 @@ entry:
define i32 @selectC_ult_i32(i1 %c, i32 %n, i32 %m) {
; CHECK-LABEL: selectC_ult_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -3319,11 +3319,11 @@ define i64 @selectRR_ult_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
; CHECK-NEXT: cmphs16 a2, a0
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: addi16 a2, sp, 8
; CHECK-NEXT: addi16 a0, sp, 16
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, a0
; CHECK-NEXT: ld16.w a0, (a2, 0)
; CHECK-NEXT: ld16.w a1, (a2, 4)
@ -3387,10 +3387,10 @@ define i64 @selectRI_ult_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: movi16 a1, 0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: ld16.w a2, (sp, 0)
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -3454,7 +3454,7 @@ define i64 @selectRX_ult_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: cmpnei16 a1, 0
; CHECK-NEXT: movi16 a1, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -3524,7 +3524,7 @@ define i64 @selectC_ult_i64(i1 %c, i64 %n, i64 %m) {
; CHECK-LABEL: selectC_ult_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld32.w t0, (sp, 0)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a3
; CHECK-NEXT: movt32 a2, t0
; CHECK-NEXT: mov16 a0, a1
@ -3710,7 +3710,7 @@ entry:
define i16 @selectC_ult_i16(i1 %c, i16 %n, i16 %m) {
; CHECK-LABEL: selectC_ult_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -3841,7 +3841,7 @@ entry:
define i8 @selectC_ult_i8(i1 %c, i8 %n, i8 %m) {
; CHECK-LABEL: selectC_ult_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -3868,9 +3868,9 @@ entry:
define i1 @selectRR_ult_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
; CHECK-LABEL: selectRR_ult_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a3, a2
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a2, a3
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
@ -3928,7 +3928,7 @@ entry:
define i1 @selectRX_ult_i1(i1 %x, i1 %n, i1 %m) {
; CHECK-LABEL: selectRX_ult_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a2, a1
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
@ -3955,7 +3955,7 @@ entry:
define i1 @selectC_ult_i1(i1 %c, i1 %n, i1 %m) {
; CHECK-LABEL: selectC_ult_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -4087,7 +4087,7 @@ entry:
define i32 @selectC_ule_i32(i1 %c, i32 %n, i32 %m) {
; CHECK-LABEL: selectC_ule_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -4126,17 +4126,17 @@ define i64 @selectRR_ule_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: st16.w a0, (sp, 8)
; CHECK-NEXT: ld16.w a0, (sp, 4)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mvc32 a0
; CHECK-NEXT: ld16.w a1, (sp, 12)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: addi16 a2, sp, 16
; CHECK-NEXT: addi16 a0, sp, 24
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, a0
; CHECK-NEXT: ld16.w a0, (a2, 0)
; CHECK-NEXT: ld16.w a1, (a2, 4)
@ -4207,10 +4207,10 @@ define i64 @selectRI_ule_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: movi16 a1, 0
; CHECK-NEXT: ld16.w a2, (sp, 4)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: ld16.w a2, (sp, 0)
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -4274,7 +4274,7 @@ define i64 @selectRX_ule_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: cmpnei16 a1, 0
; CHECK-NEXT: movi16 a1, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -4344,7 +4344,7 @@ define i64 @selectC_ule_i64(i1 %c, i64 %n, i64 %m) {
; CHECK-LABEL: selectC_ule_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld32.w t0, (sp, 0)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a3
; CHECK-NEXT: movt32 a2, t0
; CHECK-NEXT: mov16 a0, a1
@ -4532,7 +4532,7 @@ entry:
define i16 @selectC_ule_i16(i1 %c, i16 %n, i16 %m) {
; CHECK-LABEL: selectC_ule_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -4665,7 +4665,7 @@ entry:
define i8 @selectC_ule_i8(i1 %c, i8 %n, i8 %m) {
; CHECK-LABEL: selectC_ule_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -4692,10 +4692,10 @@ entry:
define i1 @selectRR_ule_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
; CHECK-LABEL: selectRR_ule_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mov16 a1, a3
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a3
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -4727,7 +4727,7 @@ entry:
define i1 @selectRI_ule_i1(i1 %x, i1 %n, i1 %m) {
; CHECK-LABEL: selectRI_ule_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a2, a1
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
@ -4774,7 +4774,7 @@ entry:
define i1 @selectC_ule_i1(i1 %c, i1 %n, i1 %m) {
; CHECK-LABEL: selectC_ule_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -4913,7 +4913,7 @@ entry:
define i32 @selectC_sgt_i32(i1 %c, i32 %n, i32 %m) {
; CHECK-LABEL: selectC_sgt_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -4951,14 +4951,14 @@ define i64 @selectRR_sgt_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
; CHECK-NEXT: cmphs16 a0, a2
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: addi16 a2, sp, 12
; CHECK-NEXT: addi16 a0, sp, 20
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, a0
; CHECK-NEXT: ld16.w a0, (a2, 0)
; CHECK-NEXT: ld16.w a1, (a2, 4)
@ -5029,12 +5029,12 @@ define i64 @selectRI_sgt_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: st16.w a1, (sp, 4)
; CHECK-NEXT: ld16.w a1, (sp, 8)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w l0, (sp, 4)
; CHECK-NEXT: btsti32 l0, 0
; CHECK-NEXT: btsti16 l0, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -5119,12 +5119,12 @@ define i64 @selectRX_sgt_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: st16.w a1, (sp, 4)
; CHECK-NEXT: ld16.w a1, (sp, 8)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w l0, (sp, 4)
; CHECK-NEXT: btsti32 l0, 0
; CHECK-NEXT: btsti16 l0, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -5202,7 +5202,7 @@ define i64 @selectC_sgt_i64(i1 %c, i64 %n, i64 %m) {
; CHECK-LABEL: selectC_sgt_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld32.w t0, (sp, 0)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a3
; CHECK-NEXT: movt32 a2, t0
; CHECK-NEXT: mov16 a0, a1
@ -5355,7 +5355,7 @@ entry:
define i16 @selectC_sgt_i16(i1 %c, i16 %n, i16 %m) {
; CHECK-LABEL: selectC_sgt_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -5503,7 +5503,7 @@ entry:
define i8 @selectC_sgt_i8(i1 %c, i8 %n, i8 %m) {
; CHECK-LABEL: selectC_sgt_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -5530,9 +5530,9 @@ entry:
define i1 @selectRR_sgt_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
; CHECK-LABEL: selectRR_sgt_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a3, a2
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a2, a3
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
@ -5590,7 +5590,7 @@ entry:
define i1 @selectRX_sgt_i1(i1 %x, i1 %n, i1 %m) {
; CHECK-LABEL: selectRX_sgt_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a2, a1
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
@ -5617,7 +5617,7 @@ entry:
define i1 @selectC_sgt_i1(i1 %c, i1 %n, i1 %m) {
; CHECK-LABEL: selectC_sgt_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -5754,7 +5754,7 @@ entry:
define i32 @selectC_sge_i32(i1 %c, i32 %n, i32 %m) {
; CHECK-LABEL: selectC_sge_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -5792,14 +5792,14 @@ define i64 @selectRR_sge_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
; CHECK-NEXT: cmplt16 a3, a1
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 a1, sp, 12
; CHECK-NEXT: addi16 a2, sp, 20
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: ld16.w a0, (a1, 0)
; CHECK-NEXT: ld16.w a1, (a1, 4)
@ -5865,12 +5865,12 @@ define i64 @selectRI_sge_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: st16.w a1, (sp, 4)
; CHECK-NEXT: ld16.w a1, (sp, 8)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w l0, (sp, 4)
; CHECK-NEXT: btsti32 l0, 0
; CHECK-NEXT: btsti16 l0, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -5955,12 +5955,12 @@ define i64 @selectRX_sge_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: st16.w a1, (sp, 4)
; CHECK-NEXT: ld16.w a1, (sp, 8)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w l0, (sp, 4)
; CHECK-NEXT: btsti32 l0, 0
; CHECK-NEXT: btsti16 l0, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -6038,7 +6038,7 @@ define i64 @selectC_sge_i64(i1 %c, i64 %n, i64 %m) {
; CHECK-LABEL: selectC_sge_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld32.w t0, (sp, 0)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a3
; CHECK-NEXT: movt32 a2, t0
; CHECK-NEXT: mov16 a0, a1
@ -6189,7 +6189,7 @@ entry:
define i16 @selectC_sge_i16(i1 %c, i16 %n, i16 %m) {
; CHECK-LABEL: selectC_sge_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -6335,7 +6335,7 @@ entry:
define i8 @selectC_sge_i8(i1 %c, i8 %n, i8 %m) {
; CHECK-LABEL: selectC_sge_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -6362,10 +6362,10 @@ entry:
define i1 @selectRR_sge_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
; CHECK-LABEL: selectRR_sge_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mov16 a1, a3
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a3
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -6397,7 +6397,7 @@ entry:
define i1 @selectRI_sge_i1(i1 %x, i1 %n, i1 %m) {
; CHECK-LABEL: selectRI_sge_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a2, a1
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
@ -6444,7 +6444,7 @@ entry:
define i1 @selectC_sge_i1(i1 %c, i1 %n, i1 %m) {
; CHECK-LABEL: selectC_sge_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -6581,7 +6581,7 @@ entry:
define i32 @selectC_slt_i32(i1 %c, i32 %n, i32 %m) {
; CHECK-LABEL: selectC_slt_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -6619,14 +6619,14 @@ define i64 @selectRR_slt_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
; CHECK-NEXT: cmphs16 a2, a0
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: addi16 a2, sp, 12
; CHECK-NEXT: addi16 a0, sp, 20
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, a0
; CHECK-NEXT: ld16.w a0, (a2, 0)
; CHECK-NEXT: ld16.w a1, (a2, 4)
@ -6696,12 +6696,12 @@ define i64 @selectRI_slt_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: cmphsi16 a0, 10
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w l0, (sp, 8)
; CHECK-NEXT: btsti32 l0, 0
; CHECK-NEXT: btsti16 l0, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -6782,12 +6782,12 @@ define i64 @selectRX_slt_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: st16.w a1, (sp, 4)
; CHECK-NEXT: ld16.w a1, (sp, 8)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w l0, (sp, 4)
; CHECK-NEXT: btsti32 l0, 0
; CHECK-NEXT: btsti16 l0, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -6865,7 +6865,7 @@ define i64 @selectC_slt_i64(i1 %c, i64 %n, i64 %m) {
; CHECK-LABEL: selectC_slt_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld32.w t0, (sp, 0)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a3
; CHECK-NEXT: movt32 a2, t0
; CHECK-NEXT: mov16 a0, a1
@ -7015,7 +7015,7 @@ entry:
define i16 @selectC_slt_i16(i1 %c, i16 %n, i16 %m) {
; CHECK-LABEL: selectC_slt_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -7161,7 +7161,7 @@ entry:
define i8 @selectC_slt_i8(i1 %c, i8 %n, i8 %m) {
; CHECK-LABEL: selectC_slt_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -7188,9 +7188,9 @@ entry:
define i1 @selectRR_slt_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
; CHECK-LABEL: selectRR_slt_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a3, a2
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, a3
; CHECK-NEXT: mov16 a0, a2
; CHECK-NEXT: rts16
@ -7226,7 +7226,7 @@ entry:
define i1 @selectRI_slt_i1(i1 %x, i1 %n, i1 %m) {
; CHECK-LABEL: selectRI_slt_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -7273,7 +7273,7 @@ entry:
define i1 @selectC_slt_i1(i1 %c, i1 %n, i1 %m) {
; CHECK-LABEL: selectC_slt_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -7407,7 +7407,7 @@ entry:
define i32 @selectC_sle_i32(i1 %c, i32 %n, i32 %m) {
; CHECK-LABEL: selectC_sle_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -7445,14 +7445,14 @@ define i64 @selectRR_sle_i64(i64 %x, i64 %y, i64 %n, i64 %m) {
; CHECK-NEXT: cmplt16 a1, a3
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w a2, (sp, 8)
; CHECK-NEXT: btsti32 a2, 0
; CHECK-NEXT: btsti16 a2, 0
; CHECK-NEXT: movf32 a0, a1
; CHECK-NEXT: addi16 a1, sp, 12
; CHECK-NEXT: addi16 a2, sp, 20
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: ld16.w a0, (a1, 0)
; CHECK-NEXT: ld16.w a1, (a1, 4)
@ -7517,12 +7517,12 @@ define i64 @selectRI_sle_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: cmphsi16 a0, 11
; CHECK-NEXT: mvcv16 a0
; CHECK-NEXT: ld16.w a1, (sp, 4)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w l0, (sp, 8)
; CHECK-NEXT: btsti32 l0, 0
; CHECK-NEXT: btsti16 l0, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -7603,12 +7603,12 @@ define i64 @selectRX_sle_i64(i64 %x, i64 %n, i64 %m) {
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: st16.w a1, (sp, 4)
; CHECK-NEXT: ld16.w a1, (sp, 8)
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: mvc32 a1
; CHECK-NEXT: ld16.w l0, (sp, 4)
; CHECK-NEXT: btsti32 l0, 0
; CHECK-NEXT: btsti16 l0, 0
; CHECK-NEXT: movf32 a1, a0
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a2, t1
; CHECK-NEXT: movt32 a3, t0
; CHECK-NEXT: mov16 a0, a2
@ -7686,7 +7686,7 @@ define i64 @selectC_sle_i64(i1 %c, i64 %n, i64 %m) {
; CHECK-LABEL: selectC_sle_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: ld32.w t0, (sp, 0)
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a3
; CHECK-NEXT: movt32 a2, t0
; CHECK-NEXT: mov16 a0, a1
@ -7834,7 +7834,7 @@ entry:
define i16 @selectC_sle_i16(i1 %c, i16 %n, i16 %m) {
; CHECK-LABEL: selectC_sle_i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -7978,7 +7978,7 @@ entry:
define i8 @selectC_sle_i8(i1 %c, i8 %n, i8 %m) {
; CHECK-LABEL: selectC_sle_i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -8005,10 +8005,10 @@ entry:
define i1 @selectRR_sle_i1(i1 %x, i1 %y, i1 %n, i1 %m) {
; CHECK-LABEL: selectRR_sle_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: mov16 a0, a3
; CHECK-NEXT: movt32 a0, a2
; CHECK-NEXT: btsti32 a1, 0
; CHECK-NEXT: btsti16 a1, 0
; CHECK-NEXT: movt32 a0, a3
; CHECK-NEXT: rts16
;
@ -8059,7 +8059,7 @@ entry:
define i1 @selectRX_sle_i1(i1 %x, i1 %n, i1 %m) {
; CHECK-LABEL: selectRX_sle_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16
@ -8086,7 +8086,7 @@ entry:
define i1 @selectC_sle_i1(i1 %c, i1 %n, i1 %m) {
; CHECK-LABEL: selectC_sle_i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: btsti32 a0, 0
; CHECK-NEXT: btsti16 a0, 0
; CHECK-NEXT: movt32 a1, a2
; CHECK-NEXT: mov16 a0, a1
; CHECK-NEXT: rts16