From 70aa568c4e71494afa5719802f5fb7f0147ec808 Mon Sep 17 00:00:00 2001 From: Sanjay Patel Date: Mon, 6 Jun 2016 15:55:00 +0000 Subject: [PATCH] regenerate checks llvm-svn: 271903 --- llvm/test/Transforms/InstCombine/exact.ll | 143 +++++++++++++--------- 1 file changed, 86 insertions(+), 57 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/exact.ll b/llvm/test/Transforms/InstCombine/exact.ll index 3670d38a02b0..73b1e044a150 100644 --- a/llvm/test/Transforms/InstCombine/exact.ll +++ b/llvm/test/Transforms/InstCombine/exact.ll @@ -1,109 +1,124 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -instcombine -S | FileCheck %s -; CHECK-LABEL: @sdiv1( -; CHECK: sdiv i32 %x, 8 define i32 @sdiv1(i32 %x) { +; CHECK-LABEL: @sdiv1( +; CHECK-NEXT: [[Y:%.*]] = sdiv i32 %x, 8 +; CHECK-NEXT: ret i32 [[Y]] +; %y = sdiv i32 %x, 8 ret i32 %y } -; CHECK-LABEL: @sdiv2( -; CHECK: ashr exact i32 %x, 3 define i32 @sdiv2(i32 %x) { +; CHECK-LABEL: @sdiv2( +; CHECK-NEXT: [[Y:%.*]] = ashr exact i32 %x, 3 +; CHECK-NEXT: ret i32 [[Y]] +; %y = sdiv exact i32 %x, 8 ret i32 %y } -; CHECK-LABEL: @sdiv3( -; CHECK: %y = srem i32 %x, 3 -; CHECK: %z = sub i32 %x, %y -; CHECK: ret i32 %z define i32 @sdiv3(i32 %x) { +; CHECK-LABEL: @sdiv3( +; CHECK-NEXT: [[Y:%.*]] = srem i32 %x, 3 +; CHECK-NEXT: [[Z:%.*]] = sub i32 %x, [[Y]] +; CHECK-NEXT: ret i32 [[Z]] +; %y = sdiv i32 %x, 3 %z = mul i32 %y, 3 ret i32 %z } -; CHECK-LABEL: @sdiv4( -; CHECK: ret i32 %x define i32 @sdiv4(i32 %x) { +; CHECK-LABEL: @sdiv4( +; CHECK-NEXT: ret i32 %x +; %y = sdiv exact i32 %x, 3 %z = mul i32 %y, 3 ret i32 %z } -; CHECK: i32 @sdiv5 -; CHECK: %y = srem i32 %x, 3 -; CHECK: %z = sub i32 %y, %x -; CHECK: ret i32 %z define i32 @sdiv5(i32 %x) { +; CHECK-LABEL: @sdiv5( +; CHECK-NEXT: [[Y:%.*]] = srem i32 %x, 3 +; CHECK-NEXT: [[Z:%.*]] = sub i32 [[Y]], %x +; CHECK-NEXT: ret i32 [[Z]] +; %y = sdiv i32 %x, 3 %z = mul i32 %y, -3 ret i32 %z } -; CHECK-LABEL: @sdiv6( -; CHECK: %z = sub i32 0, %x -; CHECK: ret i32 %z define i32 @sdiv6(i32 %x) { +; CHECK-LABEL: @sdiv6( +; CHECK-NEXT: [[Z:%.*]] = sub i32 0, %x +; CHECK-NEXT: ret i32 [[Z]] +; %y = sdiv exact i32 %x, 3 %z = mul i32 %y, -3 ret i32 %z } -; CHECK-LABEL: @udiv1( -; CHECK: ret i32 %x define i32 @udiv1(i32 %x, i32 %w) { +; CHECK-LABEL: @udiv1( +; CHECK-NEXT: ret i32 %x +; %y = udiv exact i32 %x, %w %z = mul i32 %y, %w ret i32 %z } -; CHECK-LABEL: @udiv2( -; CHECK: %z = lshr exact i32 %x, %w -; CHECK: ret i32 %z define i32 @udiv2(i32 %x, i32 %w) { +; CHECK-LABEL: @udiv2( +; CHECK-NEXT: [[Z:%.*]] = lshr exact i32 %x, %w +; CHECK-NEXT: ret i32 [[Z]] +; %y = shl i32 1, %w %z = udiv exact i32 %x, %y ret i32 %z } -; CHECK-LABEL: @ashr1( -; CHECK: %B = ashr exact i64 %A, 2 -; CHECK: ret i64 %B define i64 @ashr1(i64 %X) nounwind { +; CHECK-LABEL: @ashr1( +; CHECK-NEXT: [[A:%.*]] = shl i64 %X, 8 +; CHECK-NEXT: [[B:%.*]] = ashr exact i64 [[A]], 2 +; CHECK-NEXT: ret i64 [[B]] +; %A = shl i64 %X, 8 %B = ashr i64 %A, 2 ; X/4 ret i64 %B } ; PR9120 -; CHECK-LABEL: @ashr_icmp1( -; CHECK: %B = icmp eq i64 %X, 0 -; CHECK: ret i1 %B define i1 @ashr_icmp1(i64 %X) nounwind { +; CHECK-LABEL: @ashr_icmp1( +; CHECK-NEXT: [[B:%.*]] = icmp eq i64 %X, 0 +; CHECK-NEXT: ret i1 [[B]] +; %A = ashr exact i64 %X, 2 ; X/4 %B = icmp eq i64 %A, 0 ret i1 %B } -; CHECK-LABEL: @ashr_icmp2( -; CHECK: %Z = icmp slt i64 %X, 16 -; CHECK: ret i1 %Z define i1 @ashr_icmp2(i64 %X) nounwind { - %Y = ashr exact i64 %X, 2 ; x / 4 - %Z = icmp slt i64 %Y, 4 ; x < 16 - ret i1 %Z +; CHECK-LABEL: @ashr_icmp2( +; CHECK-NEXT: [[Z:%.*]] = icmp slt i64 %X, 16 +; CHECK-NEXT: ret i1 [[Z]] +; + %Y = ashr exact i64 %X, 2 ; x / 4 + %Z = icmp slt i64 %Y, 4 ; x < 16 + ret i1 %Z } ; PR9998 ; Make sure we don't transform the ashr here into an sdiv -; CHECK-LABEL: @pr9998( -; CHECK: [[BIT:%[A-Za-z0-9.]+]] = and i32 %V, 1 -; CHECK-NEXT: [[CMP:%[A-Za-z0-9.]+]] = icmp ne i32 [[BIT]], 0 -; CHECK-NEXT: ret i1 [[CMP]] define i1 @pr9998(i32 %V) nounwind { -entry: +; CHECK-LABEL: @pr9998( +; CHECK-NEXT: [[W_MASK:%.*]] = and i32 %V, 1 +; CHECK-NEXT: [[Z:%.*]] = icmp ne i32 [[W_MASK]], 0 +; CHECK-NEXT: ret i1 [[Z]] +; %W = shl i32 %V, 31 %X = ashr exact i32 %W, 31 %Y = sext i32 %X to i64 @@ -111,67 +126,81 @@ entry: ret i1 %Z } - - +define i1 @udiv_icmp1(i64 %X) { ; CHECK-LABEL: @udiv_icmp1( -; CHECK: icmp ne i64 %X, 0 -define i1 @udiv_icmp1(i64 %X) nounwind { +; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 %X, 0 +; CHECK-NEXT: ret i1 [[TMP1]] +; %A = udiv exact i64 %X, 5 ; X/5 %B = icmp ne i64 %A, 0 ret i1 %B } +define i1 @udiv_icmp2(i64 %X) { ; CHECK-LABEL: @udiv_icmp2( -; CHECK: icmp eq i64 %X, 0 -define i1 @udiv_icmp2(i64 %X) nounwind { +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 0 +; CHECK-NEXT: ret i1 [[TMP1]] +; %A = udiv exact i64 %X, 5 ; X/5 == 0 --> x == 0 %B = icmp eq i64 %A, 0 ret i1 %B } +define i1 @sdiv_icmp1(i64 %X) { ; CHECK-LABEL: @sdiv_icmp1( -; CHECK: icmp eq i64 %X, 0 -define i1 @sdiv_icmp1(i64 %X) nounwind { +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 0 +; CHECK-NEXT: ret i1 [[TMP1]] +; %A = sdiv exact i64 %X, 5 ; X/5 == 0 --> x == 0 %B = icmp eq i64 %A, 0 ret i1 %B } +define i1 @sdiv_icmp2(i64 %X) { ; CHECK-LABEL: @sdiv_icmp2( -; CHECK: icmp eq i64 %X, 5 -define i1 @sdiv_icmp2(i64 %X) nounwind { +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 5 +; CHECK-NEXT: ret i1 [[TMP1]] +; %A = sdiv exact i64 %X, 5 ; X/5 == 1 --> x == 5 %B = icmp eq i64 %A, 1 ret i1 %B } +define i1 @sdiv_icmp3(i64 %X) { ; CHECK-LABEL: @sdiv_icmp3( -; CHECK: icmp eq i64 %X, -5 -define i1 @sdiv_icmp3(i64 %X) nounwind { +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, -5 +; CHECK-NEXT: ret i1 [[TMP1]] +; %A = sdiv exact i64 %X, 5 ; X/5 == -1 --> x == -5 %B = icmp eq i64 %A, -1 ret i1 %B } +define i1 @sdiv_icmp4(i64 %X) { ; CHECK-LABEL: @sdiv_icmp4( -; CHECK: icmp eq i64 %X, 0 -define i1 @sdiv_icmp4(i64 %X) nounwind { +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 0 +; CHECK-NEXT: ret i1 [[TMP1]] +; %A = sdiv exact i64 %X, -5 ; X/-5 == 0 --> x == 0 %B = icmp eq i64 %A, 0 ret i1 %B } +define i1 @sdiv_icmp5(i64 %X) { ; CHECK-LABEL: @sdiv_icmp5( -; CHECK: icmp eq i64 %X, -5 -define i1 @sdiv_icmp5(i64 %X) nounwind { +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, -5 +; CHECK-NEXT: ret i1 [[TMP1]] +; %A = sdiv exact i64 %X, -5 ; X/-5 == 1 --> x == -5 %B = icmp eq i64 %A, 1 ret i1 %B } +define i1 @sdiv_icmp6(i64 %X) { ; CHECK-LABEL: @sdiv_icmp6( -; CHECK: icmp eq i64 %X, 5 -define i1 @sdiv_icmp6(i64 %X) nounwind { +; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 %X, 5 +; CHECK-NEXT: ret i1 [[TMP1]] +; %A = sdiv exact i64 %X, -5 ; X/-5 == 1 --> x == 5 %B = icmp eq i64 %A, -1 ret i1 %B