diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index 6b4f53428256..86c877efb781 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -253,7 +253,8 @@ static bool isUnsafeToMoveAcross(MachineInstr &MI, unsigned UseReg, const TargetRegisterInfo *TRI) { return (UseReg && (MI.modifiesRegister(UseReg, TRI))) || MI.modifiesRegister(DestReg, TRI) || MI.readsRegister(DestReg, TRI) || - MI.hasUnmodeledSideEffects() || MI.isInlineAsm() || MI.isDebugValue(); + MI.hasUnmodeledSideEffects() || MI.isInlineAsm() || + MI.isMetaInstruction(); } static unsigned UseReg(const MachineOperand& MO) { diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index fdf57a82cbd3..b314e06f4822 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -539,7 +539,7 @@ bool HexagonEarlyIfConversion::isProfitable(const FlowPattern &FP) const { return 0u; unsigned T = std::count_if(B->begin(), B->getFirstTerminator(), [](const MachineInstr &MI) { - return !MI.isDebugValue(); + return !MI.isMetaInstruction(); }); if (T < HEXAGON_PACKET_SIZE) Spare += HEXAGON_PACKET_SIZE-T; diff --git a/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp b/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp index 23d4e2610d9a..501ac2c44bb7 100644 --- a/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFixupHwLoops.cpp @@ -138,7 +138,7 @@ bool HexagonFixupHwLoops::fixupLoopInstrs(MachineFunction &MF) { MachineBasicBlock::iterator MIE = MBB.end(); while (MII != MIE) { InstOffset += HII->getSize(*MII); - if (MII->isDebugValue()) { + if (MII->isMetaInstruction()) { ++MII; continue; }