forked from OSchip/llvm-project
[Hexagon] Adding a number of vector load variants and organizing tests.
llvm-svn: 227588
This commit is contained in:
Colin LeMahieu
parent
6037dcfb8b
commit
709c0a16bb
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@ -1741,6 +1741,16 @@ defm loadri: LD_Idxd <"memw", "LDriw", IntRegs, s11_2Ext, u6_2Ext, 0b1100>;
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let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
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defm loadrd: LD_Idxd <"memd", "LDrid", DoubleRegs, s11_3Ext, u6_3Ext, 0b1110>;
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let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
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def L2_loadbsw2_io: T_load_io<"membh", IntRegs, 0b0001, s11_1Ext>;
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def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>;
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}
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let accessSize = WordAccess, opExtentAlign = 2, isCodeGenOnly = 0 in {
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def L2_loadbzw4_io: T_load_io<"memubh", DoubleRegs, 0b0101, s11_2Ext>;
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def L2_loadbsw4_io: T_load_io<"membh", DoubleRegs, 0b0111, s11_2Ext>;
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}
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// Patterns to select load-indexed (i.e. load from base+offset).
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multiclass Loadx_pat<PatFrag Load, ValueType VT, PatLeaf ImmPred,
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InstHexagon MI> {
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@ -1895,6 +1905,18 @@ defm loadri : LD_PostInc <"memw", "LDriw", IntRegs, s4_2Imm, 0b1100>;
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let accessSize = DoubleWordAccess, opExtentAlign = 3, isCodeGenOnly = 0 in
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defm loadrd : LD_PostInc <"memd", "LDrid", DoubleRegs, s4_3Imm, 0b1110>;
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// Rd=memb[u]h(Rx++#s4:1)
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// Rdd=memb[u]h(Rx++#s4:2)
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let accessSize = HalfWordAccess, opExtentAlign = 1, isCodeGenOnly = 0 in {
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def L2_loadbsw2_pi : T_load_pi <"membh", IntRegs, s4_1Imm, 0b0001>;
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def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>;
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}
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let accessSize = WordAccess, opExtentAlign = 2, hasNewValue = 0,
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isCodeGenOnly = 0 in {
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def L2_loadbsw4_pi : T_load_pi <"membh", DoubleRegs, s4_2Imm, 0b0111>;
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def L2_loadbzw4_pi : T_load_pi <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
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}
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//===----------------------------------------------------------------------===//
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// Template class for post increment loads with register offset.
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//===----------------------------------------------------------------------===//
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@ -1927,10 +1949,14 @@ let hasNewValue = 1, isCodeGenOnly = 0 in {
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def L2_loadrh_pr : T_load_pr <"memh", IntRegs, 0b1010, HalfWordAccess>;
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def L2_loadruh_pr : T_load_pr <"memuh", IntRegs, 0b1011, HalfWordAccess>;
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def L2_loadri_pr : T_load_pr <"memw", IntRegs, 0b1100, WordAccess>;
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def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
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}
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let isCodeGenOnly = 0 in
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let isCodeGenOnly = 0 in {
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def L2_loadrd_pr : T_load_pr <"memd", DoubleRegs, 0b1110, DoubleWordAccess>;
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def L2_loadbzw4_pr : T_load_pr <"memubh", DoubleRegs, 0b0101, WordAccess>;
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}
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// Load predicate.
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let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
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@ -1982,10 +2008,16 @@ let accessSize = ByteAccess, isCodeGenOnly = 0 in {
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let accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
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def L2_loadrh_pcr : T_load_pcr <"memh", IntRegs, 0b1010>;
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def L2_loadruh_pcr : T_load_pcr <"memuh", IntRegs, 0b1011>;
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def L2_loadbsw2_pcr : T_load_pcr <"membh", IntRegs, 0b0001>;
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def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>;
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}
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let accessSize = WordAccess, isCodeGenOnly = 0 in {
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def L2_loadri_pcr : T_load_pcr <"memw", IntRegs, 0b1100>;
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let hasNewValue = 0 in {
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def L2_loadbzw4_pcr : T_load_pcr <"memubh", DoubleRegs, 0b0101>;
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def L2_loadbsw4_pcr : T_load_pcr <"membh", DoubleRegs, 0b0111>;
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}
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}
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let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
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@ -2033,12 +2065,19 @@ let accessSize = ByteAccess, isCodeGenOnly = 0 in {
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let accessSize = HalfWordAccess, isCodeGenOnly = 0 in {
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def L2_loadrh_pci : T_load_pci <"memh", IntRegs, s4_1Imm, 0b1010>;
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def L2_loadruh_pci : T_load_pci <"memuh", IntRegs, s4_1Imm, 0b1011>;
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def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>;
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def L2_loadbsw2_pci : T_load_pci <"membh", IntRegs, s4_1Imm, 0b0001>;
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}
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// Word variants of circ load
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let accessSize = WordAccess, isCodeGenOnly = 0 in
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def L2_loadri_pci : T_load_pci <"memw", IntRegs, s4_2Imm, 0b1100>;
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let accessSize = WordAccess, hasNewValue = 0, isCodeGenOnly = 0 in {
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def L2_loadbzw4_pci : T_load_pci <"memubh", DoubleRegs, s4_2Imm, 0b0101>;
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def L2_loadbsw4_pci : T_load_pci <"membh", DoubleRegs, s4_2Imm, 0b0111>;
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}
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let accessSize = DoubleWordAccess, hasNewValue = 0, isCodeGenOnly = 0 in
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def L2_loadrd_pci : T_load_pci <"memd", DoubleRegs, s4_3Imm, 0b1110>;
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@ -2094,11 +2133,16 @@ let hasNewValue =1, opNewValue = 0, isCodeGenOnly = 0 in {
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def L2_loadrub_pbr : T_load_pbr <"memub", IntRegs, ByteAccess, 0b1001>;
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def L2_loadrh_pbr : T_load_pbr <"memh", IntRegs, HalfWordAccess, 0b1010>;
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def L2_loadruh_pbr : T_load_pbr <"memuh", IntRegs, HalfWordAccess, 0b1011>;
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def L2_loadbsw2_pbr : T_load_pbr <"membh", IntRegs, HalfWordAccess, 0b0001>;
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def L2_loadbzw2_pbr : T_load_pbr <"memubh", IntRegs, HalfWordAccess, 0b0011>;
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def L2_loadri_pbr : T_load_pbr <"memw", IntRegs, WordAccess, 0b1100>;
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}
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let isCodeGenOnly = 0 in
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let isCodeGenOnly = 0 in {
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def L2_loadbzw4_pbr : T_load_pbr <"memubh", DoubleRegs, WordAccess, 0b0101>;
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def L2_loadbsw4_pbr : T_load_pbr <"membh", DoubleRegs, WordAccess, 0b0111>;
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def L2_loadrd_pbr : T_load_pbr <"memd", DoubleRegs, DoubleWordAccess, 0b1110>;
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}
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//===----------------------------------------------------------------------===//
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// LD -
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@ -335,21 +335,43 @@ def A4_combineii: ALU32Inst<(outs DoubleRegs:$Rdd), (ins s8Imm:$s8, u6Ext:$U6),
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//===----------------------------------------------------------------------===//
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// Template class for load instructions with Absolute set addressing mode.
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//===----------------------------------------------------------------------===//
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let isExtended = 1, opExtendable = 2, hasSideEffects = 0,
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validSubTargets = HasV4SubT, addrMode = AbsoluteSet in
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class T_LD_abs_set<string mnemonic, RegisterClass RC>:
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LDInst2<(outs RC:$dst1, IntRegs:$dst2),
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(ins u0AlwaysExt:$addr),
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"$dst1 = "#mnemonic#"($dst2=##$addr)",
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[]>,
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Requires<[HasV4T]>;
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let isExtended = 1, opExtendable = 2, opExtentBits = 6, addrMode = AbsoluteSet,
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hasSideEffects = 0 in
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class T_LD_abs_set<string mnemonic, RegisterClass RC, bits<4>MajOp>:
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LDInst<(outs RC:$dst1, IntRegs:$dst2),
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(ins u6Ext:$addr),
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"$dst1 = "#mnemonic#"($dst2 = #$addr)",
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[]> {
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bits<7> name;
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bits<5> dst1;
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bits<5> dst2;
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bits<6> addr;
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def LDrid_abs_set_V4 : T_LD_abs_set <"memd", DoubleRegs>;
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def LDrib_abs_set_V4 : T_LD_abs_set <"memb", IntRegs>;
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def LDriub_abs_set_V4 : T_LD_abs_set <"memub", IntRegs>;
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def LDrih_abs_set_V4 : T_LD_abs_set <"memh", IntRegs>;
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def LDriw_abs_set_V4 : T_LD_abs_set <"memw", IntRegs>;
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def LDriuh_abs_set_V4 : T_LD_abs_set <"memuh", IntRegs>;
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let IClass = 0b1001;
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let Inst{27-25} = 0b101;
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let Inst{24-21} = MajOp;
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let Inst{13-12} = 0b01;
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let Inst{4-0} = dst1;
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let Inst{20-16} = dst2;
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let Inst{11-8} = addr{5-2};
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let Inst{6-5} = addr{1-0};
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}
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let accessSize = ByteAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
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def L4_loadrb_ap : T_LD_abs_set <"memb", IntRegs, 0b1000>;
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def L4_loadrub_ap : T_LD_abs_set <"memub", IntRegs, 0b1001>;
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}
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let accessSize = HalfWordAccess, hasNewValue = 1, isCodeGenOnly = 0 in {
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def L4_loadrh_ap : T_LD_abs_set <"memh", IntRegs, 0b1010>;
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def L4_loadruh_ap : T_LD_abs_set <"memuh", IntRegs, 0b1011>;
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}
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let accessSize = WordAccess, hasNewValue = 1, isCodeGenOnly = 0 in
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def L4_loadri_ap : T_LD_abs_set <"memw", IntRegs, 0b1100>;
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let accessSize = DoubleWordAccess, isCodeGenOnly = 0 in
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def L4_loadrd_ap : T_LD_abs_set <"memd", DoubleRegs, 0b1110>;
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//===----------------------------------------------------------------------===//
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// Template classes for the non-predicated load instructions with
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@ -1199,6 +1221,16 @@ let addrMode = BaseImmOffset, InputType = "imm", isCodeGenOnly = 0 in {
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u6_2Ext, 0b10>, AddrModeRel;
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}
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//===----------------------------------------------------------------------===//
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// Post increment loads with register offset.
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//===----------------------------------------------------------------------===//
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let hasNewValue = 1, isCodeGenOnly = 0 in
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def L2_loadbsw2_pr : T_load_pr <"membh", IntRegs, 0b0001, HalfWordAccess>;
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let isCodeGenOnly = 0 in
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def L2_loadbsw4_pr : T_load_pr <"membh", DoubleRegs, 0b0111, WordAccess>;
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//===----------------------------------------------------------------------===//
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// Template class for non-predicated post increment .new stores
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// mem[bhwd](Rx++#s4:[0123])=Nt.new
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@ -1,11 +1,19 @@
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# RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
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# Hexagon Programmer's Reference Manual 11.3 JR
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# Call subroutine from register
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0x00 0xc0 0xb5 0x50
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# CHECK: callr r21
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0x00 0xc1 0x15 0x51
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# CHECK: if (p1) callr r21
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0x00 0xc3 0x35 0x51
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# CHECK: if (!p3) callr r21
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# Hint an indirect jump address
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0x00 0xc0 0xb5 0x52
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# CHECK: hintjr(r21)
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# Jump to address from register
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0x00 0xc0 0x95 0x52
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# CHECK: jumpr r21
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0x00 0xc1 0x55 0x53
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@ -1,5 +1,7 @@
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# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
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# RUN: llvm-mc -triple hexagon -disassemble < %s | FileCheck %s
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# Hexagon Programmer's Reference Manual 11.5 LD
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# Load doubleword
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0x90 0xff 0xd5 0x3a
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# CHECK: r17:16 = memd(r21 + r31<<#3)
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0x10 0xc5 0xc0 0x49
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@ -14,6 +16,8 @@
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# CHECK: r17:16 = memd(r21++m1)
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0x10 0xe0 0xd5 0x9f
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# CHECK: r17:16 = memd(r21 ++ m1:brev)
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# Load doubleword conditionally
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0xf0 0xff 0xd5 0x30
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# CHECK: if (p3) r17:16 = memd(r21+r31<<#3)
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0xf0 0xff 0xd5 0x31
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@ -45,6 +49,7 @@
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17:16 = memd(r21++#40)
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# Load byte
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0x91 0xff 0x15 0x3a
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# CHECK: r17 = memb(r21 + r31<<#3)
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0xb1 0xc2 0x00 0x49
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@ -61,6 +66,8 @@
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# CHECK: r17 = memb(r21++m1)
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0x11 0xe0 0x15 0x9f
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# CHECK: r17 = memb(r21 ++ m1:brev)
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# Load byte conditionally
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0xf1 0xff 0x15 0x30
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# CHECK: if (p3) r17 = memb(r21+r31<<#3)
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0xf1 0xff 0x15 0x31
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@ -92,6 +99,7 @@
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17 = memb(r21++#5)
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# Load halfword
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0x91 0xff 0x55 0x3a
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# CHECK: r17 = memh(r21 + r31<<#3)
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0x51 0xc5 0x40 0x49
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@ -108,6 +116,8 @@
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# CHECK: r17 = memh(r21++m1)
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0x11 0xe0 0x55 0x9f
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# CHECK: r17 = memh(r21 ++ m1:brev)
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# Load halfword conditionally
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0xf1 0xff 0x55 0x30
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# CHECK: if (p3) r17 = memh(r21+r31<<#3)
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0xf1 0xff 0x55 0x31
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@ -129,6 +139,7 @@
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17 = memh(r21++#10)
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# Load unsigned byte
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0x91 0xff 0x35 0x3a
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# CHECK: r17 = memub(r21 + r31<<#3)
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0xb1 0xc2 0x20 0x49
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@ -145,6 +156,8 @@
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# CHECK: r17 = memub(r21++m1)
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0x11 0xe0 0x35 0x9f
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# CHECK: r17 = memub(r21 ++ m1:brev)
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# Load unsigned byte conditionally
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0xf1 0xff 0x35 0x30
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# CHECK: if (p3) r17 = memub(r21+r31<<#3)
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0xf1 0xff 0x35 0x31
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@ -176,6 +189,7 @@
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17 = memub(r21++#5)
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# Load unsigned halfword
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0x91 0xff 0x75 0x3a
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# CHECK: r17 = memuh(r21 + r31<<#3)
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0x51 0xc5 0x60 0x49
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@ -192,6 +206,8 @@
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# CHECK: r17 = memuh(r21++m1)
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0x11 0xe0 0x75 0x9f
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# CHECK: r17 = memuh(r21 ++ m1:brev)
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# Load unsigned halfword conditionally
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0xf1 0xff 0x75 0x30
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# CHECK: if (p3) r17 = memuh(r21+r31<<#3)
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0xf1 0xff 0x75 0x31
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@ -223,6 +239,7 @@
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17 = memuh(r21++#10)
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# Load word
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0x91 0xff 0x95 0x3a
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# CHECK: r17 = memw(r21 + r31<<#3)
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0x91 0xc2 0x80 0x49
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@ -239,6 +256,8 @@
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# CHECK: r17 = memw(r21++m1)
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0x11 0xe0 0x95 0x9f
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# CHECK: r17 = memw(r21 ++ m1:brev)
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# Load word conditionally
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0xf1 0xff 0x95 0x30
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# CHECK: if (p3) r17 = memw(r21+r31<<#3)
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0xf1 0xff 0x95 0x31
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@ -270,8 +289,11 @@
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) r17 = memw(r21++#20)
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# Deallocate stack frame
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0x1e 0xc0 0x1e 0x90
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# CHECK: deallocframe
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# Deallocate stack frame and return
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0x1e 0xc0 0x1e 0x96
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# CHECK: dealloc_return
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0x03 0x40 0x45 0x85 0x1e 0xcb 0x1e 0x96
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@ -290,3 +312,53 @@
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0x03 0x40 0x45 0x85 0x1e 0xfb 0x1e 0x96
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# CHECK: p3 = r5
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# CHECK-NEXT: if (!p3.new) dealloc_return:t
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# Load and unpack bytes to halfwords
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0xf1 0xc3 0x35 0x90
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# CHECK: r17 = membh(r21 + #62)
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0xf1 0xc3 0x75 0x90
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# CHECK: r17 = memubh(r21 + #62)
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0xf0 0xc3 0xb5 0x90
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# CHECK: r17:16 = memubh(r21 + #124)
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0xf0 0xc3 0xf5 0x90
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# CHECK: r17:16 = membh(r21 + #124)
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0xb1 0xe0 0x35 0x98
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# CHECK: r17 = membh(r21 ++ #10:circ(m1))
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0x11 0xe2 0x35 0x98
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# CHECK: r17 = membh(r21 ++ I:circ(m1))
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0xb1 0xe0 0x75 0x98
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# CHECK: r17 = memubh(r21 ++ #10:circ(m1))
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0x11 0xe2 0x75 0x98
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# CHECK: r17 = memubh(r21 ++ I:circ(m1))
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0xb0 0xe0 0xf5 0x98
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# CHECK: r17:16 = membh(r21 ++ #20:circ(m1))
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0x10 0xe2 0xf5 0x98
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# CHECK: r17:16 = membh(r21 ++ I:circ(m1))
|
||||
0xb0 0xe0 0xb5 0x98
|
||||
# CHECK: r17:16 = memubh(r21 ++ #20:circ(m1))
|
||||
0x10 0xe2 0xb5 0x98
|
||||
# CHECK: r17:16 = memubh(r21 ++ I:circ(m1))
|
||||
0xb1 0xc0 0x35 0x9a
|
||||
# CHECK: r17 = membh(r21++#10)
|
||||
0xb1 0xc0 0x75 0x9a
|
||||
# CHECK: r17 = memubh(r21++#10)
|
||||
0xb0 0xc0 0xb5 0x9a
|
||||
# CHECK: r17:16 = memubh(r21++#20)
|
||||
0xb0 0xc0 0xf5 0x9a
|
||||
# CHECK: r17:16 = membh(r21++#20)
|
||||
0x11 0xe0 0x35 0x9c
|
||||
# CHECK: r17 = membh(r21++m1)
|
||||
0x11 0xe0 0x75 0x9c
|
||||
# CHECK: r17 = memubh(r21++m1)
|
||||
0x10 0xe0 0xf5 0x9c
|
||||
# CHECK: r17:16 = membh(r21++m1)
|
||||
0x10 0xe0 0xb5 0x9c
|
||||
# CHECK: r17:16 = memubh(r21++m1)
|
||||
0x11 0xe0 0x35 0x9e
|
||||
# CHECK: r17 = membh(r21 ++ m1:brev)
|
||||
0x11 0xe0 0x75 0x9e
|
||||
# CHECK: r17 = memubh(r21 ++ m1:brev)
|
||||
0x10 0xe0 0xb5 0x9e
|
||||
# CHECK: r17:16 = memubh(r21 ++ m1:brev)
|
||||
0x10 0xe0 0xf5 0x9e
|
||||
# CHECK: r17:16 = membh(r21 ++ m1:brev)
|
||||
|
|
|
|||
Loading…
Reference in New Issue