forked from OSchip/llvm-project
[GlobalISel] Make isel verification checks of vregs run under NDEBUG only.
llvm-svn: 356309
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@ -89,10 +89,10 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
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"instruction is not legal", *MI);
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"instruction is not legal", *MI);
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return false;
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return false;
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}
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}
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#endif
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// FIXME: We could introduce new blocks and will need to fix the outer loop.
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// FIXME: We could introduce new blocks and will need to fix the outer loop.
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// Until then, keep track of the number of blocks to assert that we don't.
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// Until then, keep track of the number of blocks to assert that we don't.
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const size_t NumBlocks = MF.size();
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const size_t NumBlocks = MF.size();
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#endif
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for (MachineBasicBlock *MBB : post_order(&MF)) {
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for (MachineBasicBlock *MBB : post_order(&MF)) {
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if (MBB->empty())
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if (MBB->empty())
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@ -144,8 +144,6 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
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}
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}
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}
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}
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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for (MachineBasicBlock &MBB : MF) {
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for (MachineBasicBlock &MBB : MF) {
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if (MBB.empty())
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if (MBB.empty())
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continue;
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continue;
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@ -177,6 +175,8 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
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}
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}
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}
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}
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#ifndef NDEBUG
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const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
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// Now that selection is complete, there are no more generic vregs. Verify
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// Now that selection is complete, there are no more generic vregs. Verify
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// that the size of the now-constrained vreg is unchanged and that it has a
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// that the size of the now-constrained vreg is unchanged and that it has a
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// register class.
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// register class.
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@ -215,7 +215,7 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
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reportGISelFailure(MF, TPC, MORE, R);
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reportGISelFailure(MF, TPC, MORE, R);
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return false;
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return false;
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}
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}
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#endif
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auto &TLI = *MF.getSubtarget().getTargetLowering();
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auto &TLI = *MF.getSubtarget().getTargetLowering();
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TLI.finalizeLowering(MF);
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TLI.finalizeLowering(MF);
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