forked from OSchip/llvm-project
[GlobalISel] Make isel verification checks of vregs run under NDEBUG only.
llvm-svn: 356309
This commit is contained in:
parent
a61641ef40
commit
7097e83dab
|
@ -89,10 +89,10 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
|
|||
"instruction is not legal", *MI);
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
// FIXME: We could introduce new blocks and will need to fix the outer loop.
|
||||
// Until then, keep track of the number of blocks to assert that we don't.
|
||||
const size_t NumBlocks = MF.size();
|
||||
#endif
|
||||
|
||||
for (MachineBasicBlock *MBB : post_order(&MF)) {
|
||||
if (MBB->empty())
|
||||
|
@ -144,8 +144,6 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
|
|||
}
|
||||
}
|
||||
|
||||
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
|
||||
|
||||
for (MachineBasicBlock &MBB : MF) {
|
||||
if (MBB.empty())
|
||||
continue;
|
||||
|
@ -177,6 +175,8 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
|
|||
}
|
||||
}
|
||||
|
||||
#ifndef NDEBUG
|
||||
const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
|
||||
// Now that selection is complete, there are no more generic vregs. Verify
|
||||
// that the size of the now-constrained vreg is unchanged and that it has a
|
||||
// register class.
|
||||
|
@ -215,7 +215,7 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
|
|||
reportGISelFailure(MF, TPC, MORE, R);
|
||||
return false;
|
||||
}
|
||||
|
||||
#endif
|
||||
auto &TLI = *MF.getSubtarget().getTargetLowering();
|
||||
TLI.finalizeLowering(MF);
|
||||
|
||||
|
|
Loading…
Reference in New Issue