forked from OSchip/llvm-project
Misc tweaks to Intel asm printing to make it more compatible with MASM.
Patch by Benedict Gaster. llvm-svn: 73753
This commit is contained in:
Eli Friedman
parent
5ca4197829
commit
707cbc4126
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@ -339,8 +339,8 @@ void X86IntelAsmPrinter::printPICJumpTableSetLabel(unsigned uid,
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}
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void X86IntelAsmPrinter::printPICLabel(const MachineInstr *MI, unsigned Op) {
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O << "\"L" << getFunctionNumber() << "$pb\"\n";
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O << "\"L" << getFunctionNumber() << "$pb\":";
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O << "L" << getFunctionNumber() << "$pb\n";
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O << "L" << getFunctionNumber() << "$pb:";
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}
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bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO,
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@ -362,7 +362,7 @@ bool X86IntelAsmPrinter::printAsmMRegister(const MachineOperand &MO,
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break;
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}
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O << '%' << TRI->getName(Reg);
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O << TRI->getName(Reg);
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return false;
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}
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@ -414,7 +414,7 @@ bool X86IntelAsmPrinter::doInitialization(Module &M) {
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Mang->markCharUnacceptable('.');
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O << "\t.686\n\t.model flat\n\n";
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O << "\t.686\n\t.MMX\n\t.XMM\n\t.model flat\n\n";
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// Emit declarations for external functions.
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for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I)
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@ -422,7 +422,7 @@ bool X86IntelAsmPrinter::doInitialization(Module &M) {
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std::string Name = Mang->getValueName(I);
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decorateName(Name, I);
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O << "\textern " ;
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O << "\tEXTERN " ;
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if (I->hasDLLImportLinkage()) {
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O << "__imp_";
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}
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@ -436,7 +436,7 @@ bool X86IntelAsmPrinter::doInitialization(Module &M) {
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if (I->isDeclaration()) {
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std::string Name = Mang->getValueName(I);
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O << "\textern " ;
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O << "\tEXTERN " ;
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if (I->hasDLLImportLinkage()) {
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O << "__imp_";
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}
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@ -471,14 +471,14 @@ bool X86IntelAsmPrinter::doFinalization(Module &M) {
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case GlobalValue::WeakAnyLinkage:
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case GlobalValue::WeakODRLinkage:
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SwitchToDataSection("");
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O << name << "?\tsegment common 'COMMON'\n";
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O << name << "?\tSEGEMNT PARA common 'COMMON'\n";
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bCustomSegment = true;
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// FIXME: the default alignment is 16 bytes, but 1, 2, 4, and 256
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// are also available.
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break;
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case GlobalValue::AppendingLinkage:
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SwitchToDataSection("");
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O << name << "?\tsegment public 'DATA'\n";
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O << name << "?\tSEGMENT PARA public 'DATA'\n";
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bCustomSegment = true;
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// FIXME: the default alignment is 16 bytes, but 1, 2, 4, and 256
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// are also available.
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@ -1735,13 +1735,13 @@ let isTwoAddress = 0 in {
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let Defs = [EFLAGS] in {
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let Uses = [CL] in {
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def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src),
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"shl{b}\t{%cl, $dst|$dst, %CL}",
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"shl{b}\t{%cl, $dst|$dst, CL}",
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[(set GR8:$dst, (shl GR8:$src, CL))]>;
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def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src),
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"shl{w}\t{%cl, $dst|$dst, %CL}",
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"shl{w}\t{%cl, $dst|$dst, CL}",
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[(set GR16:$dst, (shl GR16:$src, CL))]>, OpSize;
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def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src),
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"shl{l}\t{%cl, $dst|$dst, %CL}",
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"shl{l}\t{%cl, $dst|$dst, CL}",
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[(set GR32:$dst, (shl GR32:$src, CL))]>;
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} // Uses = [CL]
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@ -1762,13 +1762,13 @@ def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
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let isTwoAddress = 0 in {
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let Uses = [CL] in {
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def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
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"shl{b}\t{%cl, $dst|$dst, %CL}",
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"shl{b}\t{%cl, $dst|$dst, CL}",
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[(store (shl (loadi8 addr:$dst), CL), addr:$dst)]>;
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def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
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"shl{w}\t{%cl, $dst|$dst, %CL}",
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"shl{w}\t{%cl, $dst|$dst, CL}",
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[(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
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def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
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"shl{l}\t{%cl, $dst|$dst, %CL}",
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"shl{l}\t{%cl, $dst|$dst, CL}",
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[(store (shl (loadi32 addr:$dst), CL), addr:$dst)]>;
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}
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def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
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@ -1797,13 +1797,13 @@ let isTwoAddress = 0 in {
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let Uses = [CL] in {
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def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src),
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"shr{b}\t{%cl, $dst|$dst, %CL}",
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"shr{b}\t{%cl, $dst|$dst, CL}",
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[(set GR8:$dst, (srl GR8:$src, CL))]>;
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def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src),
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"shr{w}\t{%cl, $dst|$dst, %CL}",
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"shr{w}\t{%cl, $dst|$dst, CL}",
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[(set GR16:$dst, (srl GR16:$src, CL))]>, OpSize;
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def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src),
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"shr{l}\t{%cl, $dst|$dst, %CL}",
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"shr{l}\t{%cl, $dst|$dst, CL}",
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[(set GR32:$dst, (srl GR32:$src, CL))]>;
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}
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@ -1831,14 +1831,14 @@ def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
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let isTwoAddress = 0 in {
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let Uses = [CL] in {
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def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
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"shr{b}\t{%cl, $dst|$dst, %CL}",
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"shr{b}\t{%cl, $dst|$dst, CL}",
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[(store (srl (loadi8 addr:$dst), CL), addr:$dst)]>;
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def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
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"shr{w}\t{%cl, $dst|$dst, %CL}",
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"shr{w}\t{%cl, $dst|$dst, CL}",
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[(store (srl (loadi16 addr:$dst), CL), addr:$dst)]>,
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OpSize;
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def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
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"shr{l}\t{%cl, $dst|$dst, %CL}",
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"shr{l}\t{%cl, $dst|$dst, CL}",
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[(store (srl (loadi32 addr:$dst), CL), addr:$dst)]>;
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}
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def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
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@ -1866,13 +1866,13 @@ let isTwoAddress = 0 in {
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let Uses = [CL] in {
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def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src),
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"sar{b}\t{%cl, $dst|$dst, %CL}",
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"sar{b}\t{%cl, $dst|$dst, CL}",
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[(set GR8:$dst, (sra GR8:$src, CL))]>;
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def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src),
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"sar{w}\t{%cl, $dst|$dst, %CL}",
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"sar{w}\t{%cl, $dst|$dst, CL}",
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[(set GR16:$dst, (sra GR16:$src, CL))]>, OpSize;
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def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src),
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"sar{l}\t{%cl, $dst|$dst, %CL}",
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"sar{l}\t{%cl, $dst|$dst, CL}",
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[(set GR32:$dst, (sra GR32:$src, CL))]>;
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}
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@ -1901,13 +1901,13 @@ def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
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let isTwoAddress = 0 in {
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let Uses = [CL] in {
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def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
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"sar{b}\t{%cl, $dst|$dst, %CL}",
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"sar{b}\t{%cl, $dst|$dst, CL}",
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[(store (sra (loadi8 addr:$dst), CL), addr:$dst)]>;
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def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
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"sar{w}\t{%cl, $dst|$dst, %CL}",
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"sar{w}\t{%cl, $dst|$dst, CL}",
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[(store (sra (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
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def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
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"sar{l}\t{%cl, $dst|$dst, %CL}",
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"sar{l}\t{%cl, $dst|$dst, CL}",
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[(store (sra (loadi32 addr:$dst), CL), addr:$dst)]>;
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}
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def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
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@ -1938,13 +1938,13 @@ let isTwoAddress = 0 in {
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// FIXME: provide shorter instructions when imm8 == 1
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let Uses = [CL] in {
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def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
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"rol{b}\t{%cl, $dst|$dst, %CL}",
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"rol{b}\t{%cl, $dst|$dst, CL}",
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[(set GR8:$dst, (rotl GR8:$src, CL))]>;
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def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src),
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"rol{w}\t{%cl, $dst|$dst, %CL}",
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"rol{w}\t{%cl, $dst|$dst, CL}",
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[(set GR16:$dst, (rotl GR16:$src, CL))]>, OpSize;
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def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src),
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"rol{l}\t{%cl, $dst|$dst, %CL}",
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"rol{l}\t{%cl, $dst|$dst, CL}",
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[(set GR32:$dst, (rotl GR32:$src, CL))]>;
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}
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@ -1972,13 +1972,13 @@ def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
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let isTwoAddress = 0 in {
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let Uses = [CL] in {
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def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
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"rol{b}\t{%cl, $dst|$dst, %CL}",
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"rol{b}\t{%cl, $dst|$dst, CL}",
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[(store (rotl (loadi8 addr:$dst), CL), addr:$dst)]>;
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def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
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"rol{w}\t{%cl, $dst|$dst, %CL}",
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"rol{w}\t{%cl, $dst|$dst, CL}",
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[(store (rotl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
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def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
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"rol{l}\t{%cl, $dst|$dst, %CL}",
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"rol{l}\t{%cl, $dst|$dst, CL}",
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[(store (rotl (loadi32 addr:$dst), CL), addr:$dst)]>;
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}
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def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src),
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@ -2007,13 +2007,13 @@ let isTwoAddress = 0 in {
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let Uses = [CL] in {
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def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src),
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"ror{b}\t{%cl, $dst|$dst, %CL}",
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"ror{b}\t{%cl, $dst|$dst, CL}",
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[(set GR8:$dst, (rotr GR8:$src, CL))]>;
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def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src),
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"ror{w}\t{%cl, $dst|$dst, %CL}",
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"ror{w}\t{%cl, $dst|$dst, CL}",
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[(set GR16:$dst, (rotr GR16:$src, CL))]>, OpSize;
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def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src),
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"ror{l}\t{%cl, $dst|$dst, %CL}",
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"ror{l}\t{%cl, $dst|$dst, CL}",
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[(set GR32:$dst, (rotr GR32:$src, CL))]>;
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}
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@ -2041,13 +2041,13 @@ def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
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let isTwoAddress = 0 in {
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let Uses = [CL] in {
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def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
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"ror{b}\t{%cl, $dst|$dst, %CL}",
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"ror{b}\t{%cl, $dst|$dst, CL}",
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[(store (rotr (loadi8 addr:$dst), CL), addr:$dst)]>;
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def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
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"ror{w}\t{%cl, $dst|$dst, %CL}",
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"ror{w}\t{%cl, $dst|$dst, CL}",
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[(store (rotr (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
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def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
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"ror{l}\t{%cl, $dst|$dst, %CL}",
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"ror{l}\t{%cl, $dst|$dst, CL}",
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[(store (rotr (loadi32 addr:$dst), CL), addr:$dst)]>;
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}
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def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
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@ -2079,17 +2079,17 @@ let isTwoAddress = 0 in {
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// Double shift instructions (generalizations of rotate)
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let Uses = [CL] in {
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def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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"shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
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[(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))]>, TB;
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def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
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"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
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[(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))]>, TB;
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def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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"shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
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[(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))]>,
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TB, OpSize;
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def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
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"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
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[(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))]>,
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TB, OpSize;
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}
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@ -2124,11 +2124,11 @@ def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
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let isTwoAddress = 0 in {
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let Uses = [CL] in {
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def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
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"shld{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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"shld{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
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[(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
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addr:$dst)]>, TB;
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def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
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"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, CL}",
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[(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
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addr:$dst)]>, TB;
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}
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@ -2147,11 +2147,11 @@ let isTwoAddress = 0 in {
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let Uses = [CL] in {
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def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
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"shld{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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"shld{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
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[(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
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addr:$dst)]>, TB, OpSize;
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def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
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"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, %CL}",
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"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, CL}",
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[(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
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addr:$dst)]>, TB, OpSize;
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}
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@ -303,8 +303,11 @@ X86WinTargetAsmInfo::X86WinTargetAsmInfo(const X86TargetMachine &TM):
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GlobalPrefix = "_";
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CommentString = ";";
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InlineAsmStart = "; InlineAsm Start";
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InlineAsmEnd = "; InlineAsm End";
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PrivateGlobalPrefix = "$";
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AlignDirective = "\talign\t";
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AlignDirective = "\tALIGN\t";
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ZeroDirective = "\tdb\t";
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ZeroDirectiveSuffix = " dup(0)";
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AsciiDirective = "\tdb\t";
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@ -316,13 +319,15 @@ X86WinTargetAsmInfo::X86WinTargetAsmInfo(const X86TargetMachine &TM):
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HasDotTypeDotSizeDirective = false;
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HasSingleParameterDotFile = false;
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AlignmentIsInBytes = true;
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TextSection = getUnnamedSection("_text", SectionFlags::Code);
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DataSection = getUnnamedSection("_data", SectionFlags::Writeable);
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JumpTableDataSection = NULL;
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||||
SwitchToSectionDirective = "";
|
||||
TextSectionStartSuffix = "\tsegment 'CODE'";
|
||||
DataSectionStartSuffix = "\tsegment 'DATA'";
|
||||
TextSectionStartSuffix = "\tSEGMENT PARA 'CODE'";
|
||||
DataSectionStartSuffix = "\tSEGMENT PARA 'DATA'";
|
||||
SectionEndDirectiveSuffix = "\tends\n";
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue