From 703a0fbf390bae4a6c087fb28f40e0b8e21644e5 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Fri, 1 Jul 2011 17:57:27 +0000 Subject: [PATCH] Hide the call to InitMCInstrInfo into tblgen generated ctor. llvm-svn: 134244 --- llvm/include/llvm/Target/TargetInstrInfo.h | 14 +++++----- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 4 +-- llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 5 +++- llvm/lib/Target/Alpha/AlphaInstrInfo.cpp | 7 ++--- llvm/lib/Target/Alpha/AlphaInstrInfo.h | 5 +++- .../lib/Target/Blackfin/BlackfinInstrInfo.cpp | 4 +-- llvm/lib/Target/Blackfin/BlackfinInstrInfo.h | 5 +++- llvm/lib/Target/CellSPU/SPUInstrInfo.cpp | 4 +-- llvm/lib/Target/CellSPU/SPUInstrInfo.h | 5 +++- llvm/lib/Target/MBlaze/MBlazeInstrInfo.cpp | 4 +-- llvm/lib/Target/MBlaze/MBlazeInstrInfo.h | 5 +++- llvm/lib/Target/MSP430/MSP430InstrInfo.cpp | 4 +-- llvm/lib/Target/MSP430/MSP430InstrInfo.h | 5 +++- llvm/lib/Target/Mips/MipsInstrInfo.cpp | 4 +-- llvm/lib/Target/Mips/MipsInstrInfo.h | 5 +++- llvm/lib/Target/PTX/PTXInstrInfo.cpp | 3 ++- llvm/lib/Target/PTX/PTXInstrInfo.h | 5 +++- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 4 +-- llvm/lib/Target/PowerPC/PPCInstrInfo.h | 5 +++- llvm/lib/Target/Sparc/SparcInstrInfo.cpp | 4 +-- llvm/lib/Target/Sparc/SparcInstrInfo.h | 5 +++- llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 4 +-- llvm/lib/Target/SystemZ/SystemZInstrInfo.h | 5 +++- llvm/lib/Target/TargetInstrInfo.cpp | 7 ----- llvm/lib/Target/X86/X86InstrInfo.cpp | 14 +++++----- llvm/lib/Target/X86/X86InstrInfo.h | 5 +++- llvm/lib/Target/XCore/XCoreInstrInfo.cpp | 4 +-- llvm/lib/Target/XCore/XCoreInstrInfo.h | 5 +++- llvm/utils/TableGen/InstrInfoEmitter.cpp | 26 ++++++++++++++++++- 29 files changed, 117 insertions(+), 59 deletions(-) diff --git a/llvm/include/llvm/Target/TargetInstrInfo.h b/llvm/include/llvm/Target/TargetInstrInfo.h index 70969ebd73f5..1b6b3a7690a8 100644 --- a/llvm/include/llvm/Target/TargetInstrInfo.h +++ b/llvm/include/llvm/Target/TargetInstrInfo.h @@ -44,9 +44,11 @@ class TargetInstrInfo : public MCInstrInfo { TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT public: - TargetInstrInfo(const MCInstrDesc *desc, unsigned NumOpcodes, - int CallFrameSetupOpcode = -1, - int CallFrameDestroyOpcode = -1); + TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1) + : CallFrameSetupOpcode(CFSetupOpcode), + CallFrameDestroyOpcode(CFDestroyOpcode) { + } + virtual ~TargetInstrInfo(); /// getRegClass - Givem a machine instruction descriptor, returns the register @@ -678,11 +680,9 @@ private: /// libcodegen, not in libtarget. class TargetInstrInfoImpl : public TargetInstrInfo { protected: - TargetInstrInfoImpl(const MCInstrDesc *desc, unsigned NumOpcodes, - int CallFrameSetupOpcode = -1, + TargetInstrInfoImpl(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1) - : TargetInstrInfo(desc, NumOpcodes, - CallFrameSetupOpcode, CallFrameDestroyOpcode) {} + : TargetInstrInfo(CallFrameSetupOpcode, CallFrameDestroyOpcode) {} public: virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, MachineBasicBlock *NewDest) const; diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 9f56637cae3b..32e937238fa4 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -36,6 +36,7 @@ #include "llvm/ADT/STLExtras.h" #define GET_INSTRINFO_MC_DESC +#define GET_INSTRINFO_CTOR #include "ARMGenInstrInfo.inc" using namespace llvm; @@ -77,8 +78,7 @@ static const ARM_MLxEntry ARM_MLxTable[] = { }; ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) - : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts), - ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), + : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), Subtarget(STI) { for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h index ab93cde1c93d..f95adc4cb2f4 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h @@ -20,6 +20,9 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SmallSet.h" +#define GET_INSTRINFO_HEADER +#include "ARMGenInstrInfo.inc" + namespace llvm { class ARMSubtarget; class ARMBaseRegisterInfo; @@ -172,7 +175,7 @@ namespace ARMII { }; } -class ARMBaseInstrInfo : public TargetInstrInfoImpl { +class ARMBaseInstrInfo : public ARMGenInstrInfo { const ARMSubtarget &Subtarget; protected: diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp index 220f1672d35c..c105759ff701 100644 --- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -21,13 +21,14 @@ #include "llvm/Support/ErrorHandling.h" #define GET_INSTRINFO_MC_DESC +#define GET_INSTRINFO_CTOR #include "AlphaGenInstrInfo.inc" using namespace llvm; AlphaInstrInfo::AlphaInstrInfo() - : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts), - Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP), - RI(*this) { } + : AlphaGenInstrInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP), + RI(*this) { +} unsigned diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.h b/llvm/lib/Target/Alpha/AlphaInstrInfo.h index ee6077a4a01a..337a85cdf22d 100644 --- a/llvm/lib/Target/Alpha/AlphaInstrInfo.h +++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.h @@ -17,9 +17,12 @@ #include "llvm/Target/TargetInstrInfo.h" #include "AlphaRegisterInfo.h" +#define GET_INSTRINFO_HEADER +#include "AlphaGenInstrInfo.inc" + namespace llvm { -class AlphaInstrInfo : public TargetInstrInfoImpl { +class AlphaInstrInfo : public AlphaGenInstrInfo { const AlphaRegisterInfo RI; public: AlphaInstrInfo(); diff --git a/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp b/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp index 60da4c4d091c..0515a5f325be 100644 --- a/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp +++ b/llvm/lib/Target/Blackfin/BlackfinInstrInfo.cpp @@ -20,14 +20,14 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/Support/ErrorHandling.h" +#define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC #include "BlackfinGenInstrInfo.inc" using namespace llvm; BlackfinInstrInfo::BlackfinInstrInfo(BlackfinSubtarget &ST) - : TargetInstrInfoImpl(BlackfinInsts, array_lengthof(BlackfinInsts), - BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP), + : BlackfinGenInstrInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP), RI(ST, *this), Subtarget(ST) {} diff --git a/llvm/lib/Target/Blackfin/BlackfinInstrInfo.h b/llvm/lib/Target/Blackfin/BlackfinInstrInfo.h index fdc1029da588..d22ddf0d7313 100644 --- a/llvm/lib/Target/Blackfin/BlackfinInstrInfo.h +++ b/llvm/lib/Target/Blackfin/BlackfinInstrInfo.h @@ -17,9 +17,12 @@ #include "llvm/Target/TargetInstrInfo.h" #include "BlackfinRegisterInfo.h" +#define GET_INSTRINFO_HEADER +#include "BlackfinGenInstrInfo.inc" + namespace llvm { - class BlackfinInstrInfo : public TargetInstrInfoImpl { + class BlackfinInstrInfo : public BlackfinGenInstrInfo { const BlackfinRegisterInfo RI; const BlackfinSubtarget& Subtarget; public: diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp index 5087b4784896..93b6d4c55691 100644 --- a/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp +++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.cpp @@ -22,6 +22,7 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/MC/MCContext.h" +#define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC #include "SPUGenInstrInfo.inc" @@ -53,8 +54,7 @@ namespace { } SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm) - : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0]), - SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP), + : SPUGenInstrInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP), TM(tm), RI(*TM.getSubtargetImpl(), *this) { /* NOP */ } diff --git a/llvm/lib/Target/CellSPU/SPUInstrInfo.h b/llvm/lib/Target/CellSPU/SPUInstrInfo.h index e5e91481419a..bc1ba71f7a45 100644 --- a/llvm/lib/Target/CellSPU/SPUInstrInfo.h +++ b/llvm/lib/Target/CellSPU/SPUInstrInfo.h @@ -18,9 +18,12 @@ #include "llvm/Target/TargetInstrInfo.h" #include "SPURegisterInfo.h" +#define GET_INSTRINFO_HEADER +#include "SPUGenInstrInfo.inc" + namespace llvm { //! Cell SPU instruction information class - class SPUInstrInfo : public TargetInstrInfoImpl { + class SPUInstrInfo : public SPUGenInstrInfo { SPUTargetMachine &TM; const SPURegisterInfo RI; public: diff --git a/llvm/lib/Target/MBlaze/MBlazeInstrInfo.cpp b/llvm/lib/Target/MBlaze/MBlazeInstrInfo.cpp index a3af5d928fc6..0bd62ac52919 100644 --- a/llvm/lib/Target/MBlaze/MBlazeInstrInfo.cpp +++ b/llvm/lib/Target/MBlaze/MBlazeInstrInfo.cpp @@ -21,14 +21,14 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" +#define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC #include "MBlazeGenInstrInfo.inc" using namespace llvm; MBlazeInstrInfo::MBlazeInstrInfo(MBlazeTargetMachine &tm) - : TargetInstrInfoImpl(MBlazeInsts, array_lengthof(MBlazeInsts), - MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP), + : MBlazeGenInstrInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP), TM(tm), RI(*TM.getSubtargetImpl(), *this) {} static bool isZeroImm(const MachineOperand &op) { diff --git a/llvm/lib/Target/MBlaze/MBlazeInstrInfo.h b/llvm/lib/Target/MBlaze/MBlazeInstrInfo.h index b717da8e2bec..79f962b349bf 100644 --- a/llvm/lib/Target/MBlaze/MBlazeInstrInfo.h +++ b/llvm/lib/Target/MBlaze/MBlazeInstrInfo.h @@ -19,6 +19,9 @@ #include "llvm/Target/TargetInstrInfo.h" #include "MBlazeRegisterInfo.h" +#define GET_INSTRINFO_HEADER +#include "MBlazeGenInstrInfo.inc" + namespace llvm { namespace MBlaze { @@ -219,7 +222,7 @@ namespace MBlazeII { }; } -class MBlazeInstrInfo : public TargetInstrInfoImpl { +class MBlazeInstrInfo : public MBlazeGenInstrInfo { MBlazeTargetMachine &TM; const MBlazeRegisterInfo RI; public: diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp index bf201b015680..3738a98fd97f 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -22,14 +22,14 @@ #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Support/ErrorHandling.h" +#define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC #include "MSP430GenInstrInfo.inc" using namespace llvm; MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm) - : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts), - MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP), + : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP), RI(tm, *this), TM(tm) {} void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, diff --git a/llvm/lib/Target/MSP430/MSP430InstrInfo.h b/llvm/lib/Target/MSP430/MSP430InstrInfo.h index e885cd36a041..90013f5c2e70 100644 --- a/llvm/lib/Target/MSP430/MSP430InstrInfo.h +++ b/llvm/lib/Target/MSP430/MSP430InstrInfo.h @@ -17,6 +17,9 @@ #include "llvm/Target/TargetInstrInfo.h" #include "MSP430RegisterInfo.h" +#define GET_INSTRINFO_HEADER +#include "MSP430GenInstrInfo.inc" + namespace llvm { class MSP430TargetMachine; @@ -37,7 +40,7 @@ namespace MSP430II { }; } -class MSP430InstrInfo : public TargetInstrInfoImpl { +class MSP430InstrInfo : public MSP430GenInstrInfo { const MSP430RegisterInfo RI; MSP430TargetMachine &TM; public: diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp index deab5e5ea742..7d39be2aa7cf 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -19,14 +19,14 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Support/ErrorHandling.h" +#define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC #include "MipsGenInstrInfo.inc" using namespace llvm; MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm) - : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts), - Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), + : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), TM(tm), RI(*TM.getSubtargetImpl(), *this) {} static bool isZeroImm(const MachineOperand &op) { diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.h b/llvm/lib/Target/Mips/MipsInstrInfo.h index b7f8bec49668..d02fdc1b37ae 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.h +++ b/llvm/lib/Target/Mips/MipsInstrInfo.h @@ -19,6 +19,9 @@ #include "llvm/Target/TargetInstrInfo.h" #include "MipsRegisterInfo.h" +#define GET_INSTRINFO_HEADER +#include "MipsGenInstrInfo.inc" + namespace llvm { namespace Mips { @@ -164,7 +167,7 @@ namespace MipsII { }; } -class MipsInstrInfo : public TargetInstrInfoImpl { +class MipsInstrInfo : public MipsGenInstrInfo { MipsTargetMachine &TM; const MipsRegisterInfo RI; public: diff --git a/llvm/lib/Target/PTX/PTXInstrInfo.cpp b/llvm/lib/Target/PTX/PTXInstrInfo.cpp index 1bbd8d5bc58f..7f0fa8b23bcc 100644 --- a/llvm/lib/Target/PTX/PTXInstrInfo.cpp +++ b/llvm/lib/Target/PTX/PTXInstrInfo.cpp @@ -21,13 +21,14 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" +#define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC #include "PTXGenInstrInfo.inc" using namespace llvm; PTXInstrInfo::PTXInstrInfo(PTXTargetMachine &_TM) - : TargetInstrInfoImpl(PTXInsts, array_lengthof(PTXInsts)), + : PTXGenInstrInfo(), RI(_TM, *this), TM(_TM) {} static const struct map_entry { diff --git a/llvm/lib/Target/PTX/PTXInstrInfo.h b/llvm/lib/Target/PTX/PTXInstrInfo.h index a2eea25da975..871f1ac8d376 100644 --- a/llvm/lib/Target/PTX/PTXInstrInfo.h +++ b/llvm/lib/Target/PTX/PTXInstrInfo.h @@ -17,6 +17,9 @@ #include "PTXRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" +#define GET_INSTRINFO_HEADER +#include "PTXGenInstrInfo.inc" + namespace llvm { class PTXTargetMachine; @@ -24,7 +27,7 @@ class MachineSDNode; class SDValue; class SelectionDAG; -class PTXInstrInfo : public TargetInstrInfoImpl { +class PTXInstrInfo : public PTXGenInstrInfo { private: const PTXRegisterInfo RI; PTXTargetMachine &TM; diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index 1ddc0f0e56e2..5b740b91a62b 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -28,6 +28,7 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/MC/MCAsmInfo.h" +#define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC #include "PPCGenInstrInfo.inc" @@ -39,8 +40,7 @@ extern cl::opt EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. using namespace llvm; PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) - : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts), - PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), + : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), TM(tm), RI(*TM.getSubtargetImpl(), *this) {} /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.h b/llvm/lib/Target/PowerPC/PPCInstrInfo.h index b5249ae03769..90bacc96c87e 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.h +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.h @@ -18,6 +18,9 @@ #include "llvm/Target/TargetInstrInfo.h" #include "PPCRegisterInfo.h" +#define GET_INSTRINFO_HEADER +#include "PPCGenInstrInfo.inc" + namespace llvm { /// PPCII - This namespace holds all of the PowerPC target-specific @@ -61,7 +64,7 @@ enum PPC970_Unit { } // end namespace PPCII -class PPCInstrInfo : public TargetInstrInfoImpl { +class PPCInstrInfo : public PPCGenInstrInfo { PPCTargetMachine &TM; const PPCRegisterInfo RI; diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp index e555b79480b9..17a41f2c9fa0 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.cpp +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.cpp @@ -21,14 +21,14 @@ #include "llvm/Support/ErrorHandling.h" #include "SparcMachineFunctionInfo.h" +#define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC #include "SparcGenInstrInfo.inc" using namespace llvm; SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) - : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts), - SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), + : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(ST, *this), Subtarget(ST) { } diff --git a/llvm/lib/Target/Sparc/SparcInstrInfo.h b/llvm/lib/Target/Sparc/SparcInstrInfo.h index b2d24f52503b..eda64efb7a03 100644 --- a/llvm/lib/Target/Sparc/SparcInstrInfo.h +++ b/llvm/lib/Target/Sparc/SparcInstrInfo.h @@ -17,6 +17,9 @@ #include "llvm/Target/TargetInstrInfo.h" #include "SparcRegisterInfo.h" +#define GET_INSTRINFO_HEADER +#include "SparcGenInstrInfo.inc" + namespace llvm { /// SPII - This namespace holds all of the target specific flags that @@ -31,7 +34,7 @@ namespace SPII { }; } -class SparcInstrInfo : public TargetInstrInfoImpl { +class SparcInstrInfo : public SparcGenInstrInfo { const SparcRegisterInfo RI; const SparcSubtarget& Subtarget; public: diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index 71ba9f9e7f89..fae9a6a6157d 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -23,14 +23,14 @@ #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Support/ErrorHandling.h" +#define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC #include "SystemZGenInstrInfo.inc" using namespace llvm; SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm) - : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts), - SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN), + : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN), RI(tm, *this), TM(tm) { } diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h index a39c21e43611..6a31e9496365 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h @@ -19,6 +19,9 @@ #include "llvm/ADT/IndexedMap.h" #include "llvm/Target/TargetInstrInfo.h" +#define GET_INSTRINFO_HEADER +#include "SystemZGenInstrInfo.inc" + namespace llvm { class SystemZTargetMachine; @@ -47,7 +50,7 @@ namespace SystemZII { }; } -class SystemZInstrInfo : public TargetInstrInfoImpl { +class SystemZInstrInfo : public SystemZGenInstrInfo { const SystemZRegisterInfo RI; SystemZTargetMachine &TM; public: diff --git a/llvm/lib/Target/TargetInstrInfo.cpp b/llvm/lib/Target/TargetInstrInfo.cpp index 2931416febb0..d52ecb32cf75 100644 --- a/llvm/lib/Target/TargetInstrInfo.cpp +++ b/llvm/lib/Target/TargetInstrInfo.cpp @@ -24,13 +24,6 @@ using namespace llvm; // TargetInstrInfo //===----------------------------------------------------------------------===// -TargetInstrInfo::TargetInstrInfo(const MCInstrDesc* Desc, unsigned numOpcodes, - int CFSetupOpcode, int CFDestroyOpcode) - : CallFrameSetupOpcode(CFSetupOpcode), - CallFrameDestroyOpcode(CFDestroyOpcode) { - InitMCInstrInfo(Desc, numOpcodes); -} - TargetInstrInfo::~TargetInstrInfo() { } diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index d44bd35fdc0e..702331d8ed99 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -35,6 +35,7 @@ #include "llvm/MC/MCAsmInfo.h" #include +#define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC #include "X86GenInstrInfo.inc" @@ -54,13 +55,12 @@ ReMatPICStubLoad("remat-pic-stub-load", cl::init(false), cl::Hidden); X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) - : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts), - (tm.getSubtarget().is64Bit() - ? X86::ADJCALLSTACKDOWN64 - : X86::ADJCALLSTACKDOWN32), - (tm.getSubtarget().is64Bit() - ? X86::ADJCALLSTACKUP64 - : X86::ADJCALLSTACKUP32)), + : X86GenInstrInfo((tm.getSubtarget().is64Bit() + ? X86::ADJCALLSTACKDOWN64 + : X86::ADJCALLSTACKDOWN32), + (tm.getSubtarget().is64Bit() + ? X86::ADJCALLSTACKUP64 + : X86::ADJCALLSTACKUP32)), TM(tm), RI(tm, *this) { enum { TB_NOT_REVERSABLE = 1U << 31, diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h index d8950230d83d..5f2eba34ac45 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.h +++ b/llvm/lib/Target/X86/X86InstrInfo.h @@ -19,6 +19,9 @@ #include "X86RegisterInfo.h" #include "llvm/ADT/DenseMap.h" +#define GET_INSTRINFO_HEADER +#include "X86GenInstrInfo.inc" + namespace llvm { class X86RegisterInfo; class X86TargetMachine; @@ -611,7 +614,7 @@ inline static bool isMem(const MachineInstr *MI, unsigned Op) { isLeaMem(MI, Op); } -class X86InstrInfo : public TargetInstrInfoImpl { +class X86InstrInfo : public X86GenInstrInfo { X86TargetMachine &TM; const X86RegisterInfo RI; diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp index cb545202edfc..c39571d3e4c2 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.cpp +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.cpp @@ -22,6 +22,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#define GET_INSTRINFO_CTOR #define GET_INSTRINFO_MC_DESC #include "XCoreGenInstrInfo.inc" @@ -40,8 +41,7 @@ namespace XCore { using namespace llvm; XCoreInstrInfo::XCoreInstrInfo() - : TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts), - XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), + : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), RI(*this) { } diff --git a/llvm/lib/Target/XCore/XCoreInstrInfo.h b/llvm/lib/Target/XCore/XCoreInstrInfo.h index 977fe8dd550a..840b1e163652 100644 --- a/llvm/lib/Target/XCore/XCoreInstrInfo.h +++ b/llvm/lib/Target/XCore/XCoreInstrInfo.h @@ -17,9 +17,12 @@ #include "llvm/Target/TargetInstrInfo.h" #include "XCoreRegisterInfo.h" +#define GET_INSTRINFO_HEADER +#include "XCoreGenInstrInfo.inc" + namespace llvm { -class XCoreInstrInfo : public TargetInstrInfoImpl { +class XCoreInstrInfo : public XCoreGenInstrInfo { const XCoreRegisterInfo RI; public: XCoreInstrInfo(); diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp index 7b90663716d9..5e2fdf059e3f 100644 --- a/llvm/utils/TableGen/InstrInfoEmitter.cpp +++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp @@ -208,7 +208,6 @@ void InstrInfoEmitter::run(raw_ostream &OS) { OperandInfoIDs, OS); OS << "};\n\n"; - // MCInstrInfo initialization routine. OS << "static inline void Init" << TargetName << "MCInstrInfo(MCInstrInfo *II) {\n"; @@ -218,6 +217,31 @@ void InstrInfoEmitter::run(raw_ostream &OS) { OS << "} // End llvm namespace \n"; OS << "#endif // GET_INSTRINFO_MC_DESC\n\n"; + + // Create a TargetInstrInfo subclass to hide the MC layer initialization. + OS << "\n#ifdef GET_INSTRINFO_HEADER\n"; + OS << "#undef GET_INSTRINFO_HEADER\n"; + + std::string ClassName = TargetName + "GenInstrInfo"; + OS << "namespace llvm {\n\n"; + OS << "struct " << ClassName << " : public TargetInstrInfoImpl {\n" + << " explicit " << ClassName << "(int SO = -1, int DO = -1);\n" + << "};\n"; + OS << "} // End llvm namespace \n"; + + OS << "#endif // GET_INSTRINFO_HEADER\n\n"; + + OS << "\n#ifdef GET_INSTRINFO_CTOR\n"; + OS << "#undef GET_INSTRINFO_CTOR\n"; + + OS << "namespace llvm {\n\n"; + OS << ClassName << "::" << ClassName << "(int SO, int DO)\n" + << " : TargetInstrInfoImpl(SO, DO) {\n" + << " InitMCInstrInfo(" << TargetName << "Insts, " + << NumberedInstructions.size() << ");\n}\n"; + OS << "} // End llvm namespace \n"; + + OS << "#endif // GET_INSTRINFO_CTOR\n\n"; } void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,