forked from OSchip/llvm-project
Add new entry/exit edges when removing delay slot nodes from the graph.
Renamed some header files. llvm-svn: 610
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3e8029dc07
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703297cf24
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@ -1,3 +1,4 @@
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// $Id$
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//***************************************************************************
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// File:
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// InstrScheduling.cpp
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@ -6,7 +7,7 @@
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//
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// History:
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// 7/23/01 - Vikram Adve - Created
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//***************************************************************************
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//**************************************************************************/
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#include "llvm/CodeGen/InstrScheduling.h"
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#include "SchedPriorities.h"
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@ -68,6 +69,7 @@ static bool NodeCanFillDelaySlot (const SchedulingManager& S,
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bool nodeIsPredecessor);
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static void MarkNodeForDelaySlot (SchedulingManager& S,
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SchedGraph* graph,
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SchedGraphNode* node,
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const SchedGraphNode* brNode,
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bool nodeIsPredecessor);
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@ -397,7 +399,6 @@ private:
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public:
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/*ctor*/ SchedulingManager (const TargetMachine& _target,
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const MachineSchedInfo &schedinfo,
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const SchedGraph* graph,
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SchedPriorities& schedPrio);
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/*dtor*/ ~SchedulingManager () {}
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@ -559,17 +560,16 @@ private:
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/*ctor*/
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SchedulingManager::SchedulingManager(const TargetMachine& target,
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const MachineSchedInfo &schedinfo,
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const SchedGraph* graph,
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SchedPriorities& _schedPrio)
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: nslots(schedinfo.getMaxNumIssueTotal()),
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schedInfo(schedinfo),
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: nslots(target.getSchedInfo().getMaxNumIssueTotal()),
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schedInfo(target.getSchedInfo()),
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schedPrio(_schedPrio),
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isched(nslots, graph->getNumNodes()),
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totalInstrCount(graph->getNumNodes() - 2),
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nextEarliestIssueTime(0),
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choicesForSlot(nslots),
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numInClass(schedinfo.getNumSchedClasses(), 0), // set all to 0
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numInClass(target.getSchedInfo().getNumSchedClasses(), 0), // set all to 0
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nextEarliestStartTime(target.getInstrInfo().getNumRealOpCodes(),
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(cycles_t) 0) // set all to 0
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{
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@ -621,8 +621,10 @@ SchedulingManager::updateEarliestStartTimes(const SchedGraphNode* node,
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// are still in SSA form.
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//---------------------------------------------------------------------------
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bool ScheduleInstructionsWithSSA(Method* method, const TargetMachine &target,
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const MachineSchedInfo &schedInfo) {
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bool
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ScheduleInstructionsWithSSA(Method* method,
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const TargetMachine &target)
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{
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SchedGraphSet graphSet(method, target);
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if (SchedDebugLevel >= Sched_PrintSchedGraphs)
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@ -644,7 +646,7 @@ bool ScheduleInstructionsWithSSA(Method* method, const TargetMachine &target,
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cout << endl << "*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
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SchedPriorities schedPrio(method, graph); // expensive!
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SchedulingManager S(target, schedInfo, graph, schedPrio);
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SchedulingManager S(target, graph, schedPrio);
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ChooseInstructionsForDelaySlots(S, bb, graph); // modifies graph
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@ -718,6 +720,7 @@ instrIsFeasible(const SchedulingManager& S,
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return true;
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}
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//************************* Internal Functions *****************************/
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@ -771,21 +774,32 @@ ForwardListSchedule(SchedulingManager& S)
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static void
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RecordSchedule(const BasicBlock* bb, const SchedulingManager& S)
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{
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MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
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const MachineInstrInfo& mii = S.schedInfo.getInstrInfo();
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#ifndef NDEBUG
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// Lets make sure we didn't lose any instructions, except possibly
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// some NOPs from delay slots. Also, PHIs are not included in the schedule.
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unsigned numInstr = 0;
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for (MachineCodeForBasicBlock::iterator I=mvec.begin(); I != mvec.end(); ++I)
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if (! mii.isNop((*I)->getOpCode()) &&
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! mii.isDummyPhiInstr((*I)->getOpCode()))
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++numInstr;
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assert(S.isched.getNumInstructions() >= numInstr &&
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"Lost some non-NOP instructions during scheduling!");
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#endif
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if (S.isched.getNumInstructions() == 0)
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return; // empty basic block!
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MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
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unsigned int oldSize = mvec.size();
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// First find the dummy instructions at the start of the basic block
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const MachineInstrInfo& mii = S.schedInfo.getInstrInfo();
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MachineCodeForBasicBlock::iterator I = mvec.begin();
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for ( ; I != mvec.end(); ++I)
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if (! mii.isDummyPhiInstr((*I)->getOpCode()))
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break;
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// Erase all except the dummy PHI instructions from mvec, and
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// pre-allocate create space for the ones we will be put back in.
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// pre-allocate create space for the ones we will put back in.
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mvec.erase(I, mvec.end());
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mvec.reserve(mvec.size() + S.isched.getNumInstructions());
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@ -801,7 +815,7 @@ ChooseOneGroup(SchedulingManager& S)
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assert(S.schedPrio.getNumReady() > 0
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&& "Don't get here without ready instructions.");
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DelaySlotInfo* getDelaySlotInfo;
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DelaySlotInfo* getDelaySlotInfo = NULL;
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// Choose up to `nslots' feasible instructions and their possible slots.
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unsigned numIssued = FindSlotChoices(S, getDelaySlotInfo);
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@ -1289,11 +1303,11 @@ ChooseInstructionsForDelaySlots(SchedulingManager& S,
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// Mark the nodes chosen for delay slots. This removes them from the graph.
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for (unsigned i=0; i < sdelayNodeVec.size(); i++)
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MarkNodeForDelaySlot(S, sdelayNodeVec[i], brNode, true);
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MarkNodeForDelaySlot(S, graph, sdelayNodeVec[i], brNode, true);
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// And remove the unused NOPs the graph.
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// And remove the unused NOPs from the graph.
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for (unsigned i=0; i < nopNodeVec.size(); i++)
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nopNodeVec[i]->eraseAllEdges();
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graph->eraseIncidentEdges(nopNodeVec[i], /*addDummyEdges*/ true);
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}
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@ -1355,14 +1369,16 @@ NodeCanFillDelaySlot(const SchedulingManager& S,
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void
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MarkNodeForDelaySlot(SchedulingManager& S,
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SchedGraph* graph,
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SchedGraphNode* node,
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const SchedGraphNode* brNode,
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bool nodeIsPredecessor)
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{
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if (nodeIsPredecessor)
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{ // If node is in the same basic block (i.e., preceeds brNode),
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// remove it and all its incident edges from the graph.
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node->eraseAllEdges();
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// remove it and all its incident edges from the graph. Make sure we
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// add dummy edges for pred/succ nodes that become entry/exit nodes.
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graph->eraseIncidentEdges(node, /*addDummyEdges*/ true);
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}
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else
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{ // If the node was from a target block, add the node to the graph
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