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ARM64: use 32-bit operations for uxtb & uxth 

Testing will be enabled shortly with basic-a64-instructions.s

llvm-svn: 207648
This commit is contained in:
Tim Northover 2014-04-30 13:37:02 +00:00
parent 32ac450f09
commit 7030f05b4f
2 changed files with 21 additions and 5 deletions
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22
llvm/lib/Target/ARM64/AsmParser/ARM64AsmParser.cpp
View File

@ -4196,9 +4196,8 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
delete Op;
}
}
// FIXME: Likewise for [su]xt[bh] with a Xd dst operand
else if (NumOperands == 3 &&
(Tok == "sxtb" || Tok == "uxtb" || Tok == "sxth" || Tok == "uxth")) {
// FIXME: Likewise for sxt[bh] with a Xd dst operand
else if (NumOperands == 3 && (Tok == "sxtb" || Tok == "sxth")) {
ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
if (Op->isReg() &&
ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(
@ -4214,6 +4213,23 @@ bool ARM64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
}
}
}
// FIXME: Likewise for uxt[bh] with a Xd dst operand
else if (NumOperands == 3 && (Tok == "uxtb" || Tok == "uxth")) {
ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
if (Op->isReg() &&
ARM64MCRegisterClasses[ARM64::GPR64allRegClassID].contains(
Op->getReg())) {
// The source register can be Wn here, but the matcher expects a
// GPR32. Twiddle it here if necessary.
ARM64Operand *Op = static_cast<ARM64Operand *>(Operands[1]);
if (Op->isReg()) {
unsigned Reg = getWRegFromXReg(Op->getReg());
Operands[1] = ARM64Operand::CreateReg(Reg, false, Op->getStartLoc(),
Op->getEndLoc(), getContext());
delete Op;
}
}
}
// Yet another horrible hack to handle FMOV Rd, #0.0 using [WX]ZR.
if (NumOperands == 3 && Tok == "fmov") {

4
llvm/test/MC/ARM64/aliases.s
View File

@ -249,8 +249,8 @@ foo:
; CHECK: sxtb x1, w2
; CHECK: sxth x1, w2
; CHECK: sxtw x1, w2
; CHECK: ubfx x1, x2, #0, #8
; CHECK: ubfx x1, x2, #0, #16
; CHECK: uxtb w1, w2
; CHECK: uxth w1, w2
; CHECK: ubfx x1, x2, #0, #32
;-----------------------------------------------------------------------------