forked from OSchip/llvm-project
AMDGPU/SI: Fix trunc i16 pattern
Hit on ASICs that support 16bit instructions. Differential Revision: https://reviews.llvm.org/D30281 llvm-svn: 295990
This commit is contained in:
Jan Vesely
parent
4c0ea9d438
commit
70293a045b
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@ -1042,6 +1042,11 @@ def : Pat <
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(V_CMP_EQ_U32_e64 (S_AND_B32 (i32 1), $a), (i32 1))
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>;
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def : Pat <
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(i1 (trunc i16:$a)),
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(V_CMP_EQ_U32_e64 (S_AND_B32 (i32 1), $a), (i32 1))
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>;
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def : Pat <
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(i1 (trunc i64:$a)),
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(V_CMP_EQ_U32_e64 (S_AND_B32 (i32 1),
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@ -607,12 +607,6 @@ def : Pat<
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(COPY $src)
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>;
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def : Pat<
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(i1 (trunc i16:$src)),
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(COPY $src)
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>;
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def : Pat <
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(i16 (trunc i64:$src)),
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(EXTRACT_SUBREG $src, sub0)
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@ -1,13 +1,15 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {
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; SI-LABEL: {{^}}trunc_i64_to_i32_store:
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; SI: s_load_dword [[SLOAD:s[0-9]+]], s[0:1], 0xb
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; SI: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]
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; GCN-LABEL: {{^}}trunc_i64_to_i32_store:
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; GCN: s_load_dword [[SLOAD:s[0-9]+]], s[0:1],
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; GCN: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]
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; SI: buffer_store_dword [[VLOAD]]
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; VI: flat_store_dword v[{{[0-9:]+}}], [[VLOAD]]
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; EG-LABEL: {{^}}trunc_i64_to_i32_store:
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; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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@ -18,12 +20,14 @@ define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {
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ret void
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}
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; SI-LABEL: {{^}}trunc_load_shl_i64:
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; SI-DAG: s_load_dwordx2
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; SI-DAG: s_load_dword [[SREG:s[0-9]+]],
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; SI: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
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; SI: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]
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; SI: buffer_store_dword [[VSHL]],
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; GCN-LABEL: {{^}}trunc_load_shl_i64:
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; GCN-DAG: s_load_dwordx2
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; GCN-DAG: s_load_dword [[SREG:s[0-9]+]],
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; GCN: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
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; GCN: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]
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; SI: buffer_store_dword [[VSHL]]
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; VI: flat_store_dword v[{{[0-9:]+}}], [[VSHL]]
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define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) {
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%b = shl i64 %a, 2
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%result = trunc i64 %b to i32
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@ -31,15 +35,17 @@ define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) {
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ret void
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}
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; SI-LABEL: {{^}}trunc_shl_i64:
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; GCN-LABEL: {{^}}trunc_shl_i64:
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; SI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
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; SI: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2
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; SI: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],
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; SI: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]
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; SI: s_addc_u32
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; VI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
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; GCN: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2
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; GCN: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],
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; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]
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; GCN: s_addc_u32
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; SI: buffer_store_dword v[[LO_VREG]],
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; SI: v_mov_b32_e32
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; SI: v_mov_b32_e32
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; VI: flat_store_dword v[{{[0-9:]+}}], v[[LO_VREG]]
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; GCN: v_mov_b32_e32
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; GCN: v_mov_b32_e32
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define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) {
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%aa = add i64 %a, 234 ; Prevent shrinking store.
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%b = shl i64 %aa, 2
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@ -49,9 +55,9 @@ define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64
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ret void
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}
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; SI-LABEL: {{^}}trunc_i32_to_i1:
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; SI: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; SI: v_cmp_eq_u32
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; GCN-LABEL: {{^}}trunc_i32_to_i1:
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; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; GCN: v_cmp_eq_u32
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define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) {
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%a = load i32, i32 addrspace(1)* %ptr, align 4
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%trunc = trunc i32 %a to i1
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@ -60,9 +66,30 @@ define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) {
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ret void
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}
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; SI-LABEL: {{^}}sgpr_trunc_i32_to_i1:
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; SI: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}
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; SI: v_cmp_eq_u32
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; GCN-LABEL: {{^}}trunc_i8_to_i1:
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; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; GCN: v_cmp_eq_u32
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define void @trunc_i8_to_i1(i8 addrspace(1)* %out, i8 addrspace(1)* %ptr) {
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%a = load i8, i8 addrspace(1)* %ptr, align 4
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%trunc = trunc i8 %a to i1
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%result = select i1 %trunc, i8 1, i8 0
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store i8 %result, i8 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}sgpr_trunc_i16_to_i1:
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; GCN: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}
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; GCN: v_cmp_eq_u32
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define void @sgpr_trunc_i16_to_i1(i16 addrspace(1)* %out, i16 %a) {
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%trunc = trunc i16 %a to i1
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%result = select i1 %trunc, i16 1, i16 0
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store i16 %result, i16 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}sgpr_trunc_i32_to_i1:
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; GCN: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}
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; GCN: v_cmp_eq_u32
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define void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {
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%trunc = trunc i32 %a to i1
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%result = select i1 %trunc, i32 1, i32 0
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@ -70,11 +97,12 @@ define void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {
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ret void
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}
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; SI-LABEL: {{^}}s_trunc_i64_to_i1:
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; GCN-LABEL: {{^}}s_trunc_i64_to_i1:
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; SI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb
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; SI: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]
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; SI: v_cmp_eq_u32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], [[MASKED]], 1{{$}}
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; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]
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; VI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x2c
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; GCN: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]
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; GCN: v_cmp_eq_u32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], [[MASKED]], 1{{$}}
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; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]
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define void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 %x) {
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%trunc = trunc i64 %x to i1
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%sel = select i1 %trunc, i32 63, i32 -12
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@ -82,11 +110,12 @@ define void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 %x) {
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ret void
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}
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; SI-LABEL: {{^}}v_trunc_i64_to_i1:
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; GCN-LABEL: {{^}}v_trunc_i64_to_i1:
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; SI: buffer_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}
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; SI: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]
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; SI: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]]
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; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc
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; VI: flat_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}
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; GCN: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]
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; GCN: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]]
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; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc
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define void @v_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 addrspace(1)* %in) {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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