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Get TargetRegisterInfo and TargetInstrInfo off of the MachineFunction 

and remove unnecessary class variables.

llvm-svn: 227832
This commit is contained in:
Eric Christopher 2015-02-02 18:46:31 +00:00
parent 12a5c0db57
commit 6ff7ed6446
3 changed files with 12 additions and 20 deletions
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3
llvm/lib/Target/Hexagon/Hexagon.h
View File

@ -39,8 +39,7 @@ namespace llvm {
FunctionPass *createHexagonSplitTFRCondSets(const HexagonTargetMachine &TM);
FunctionPass *createHexagonSplitConst32AndConst64(
const HexagonTargetMachine &TM);
FunctionPass *createHexagonExpandPredSpillCode(
const HexagonTargetMachine &TM);
FunctionPass *createHexagonExpandPredSpillCode();
FunctionPass *createHexagonHardwareLoops();
FunctionPass *createHexagonPeephole();
FunctionPass *createHexagonFixupHwLoops();

27
llvm/lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
View File

@ -20,7 +20,6 @@
#include "Hexagon.h"
#include "HexagonMachineFunctionInfo.h"
#include "HexagonSubtarget.h"
#include "HexagonTargetMachine.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/CodeGen/LatencyPriorityQueue.h"
#include "llvm/CodeGen/MachineDominators.h"
@ -49,13 +48,9 @@ namespace llvm {
namespace {
class HexagonExpandPredSpillCode : public MachineFunctionPass {
const HexagonTargetMachine& QTM;
const HexagonSubtarget &QST;
public:
static char ID;
HexagonExpandPredSpillCode(const HexagonTargetMachine& TM) :
MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {
HexagonExpandPredSpillCode() : MachineFunctionPass(ID) {
PassRegistry &Registry = *PassRegistry::getPassRegistry();
initializeHexagonExpandPredSpillCodePass(Registry);
}
@ -72,7 +67,9 @@ char HexagonExpandPredSpillCode::ID = 0;
bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
const HexagonInstrInfo *TII = QTM.getSubtargetImpl()->getInstrInfo();
const HexagonSubtarget &QST = Fn.getSubtarget<HexagonSubtarget>();
const HexagonRegisterInfo *TRI = QST.getRegisterInfo();
const HexagonInstrInfo *TII = QST.getInstrInfo();
// Loop over all of the basic blocks.
for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end();
@ -86,10 +83,8 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
if (Opc == Hexagon::STriw_pred) {
// STriw_pred [R30], ofst, SrcReg;
unsigned FP = MI->getOperand(0).getReg();
assert(
FP ==
QTM.getSubtargetImpl()->getRegisterInfo()->getFrameRegister() &&
"Not a Frame Pointer, Nor a Spill Slot");
assert(FP == TRI->getFrameRegister() &&
"Not a Frame Pointer, Nor a Spill Slot");
assert(MI->getOperand(1).isImm() && "Not an offset");
int Offset = MI->getOperand(1).getImm();
int SrcReg = MI->getOperand(2).getReg();
@ -135,10 +130,8 @@ bool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) {
assert(Hexagon::PredRegsRegClass.contains(DstReg) &&
"Not a predicate register");
unsigned FP = MI->getOperand(1).getReg();
assert(
FP ==
QTM.getSubtargetImpl()->getRegisterInfo()->getFrameRegister() &&
"Not a Frame Pointer, Nor a Spill Slot");
assert(FP == TRI->getFrameRegister() &&
"Not a Frame Pointer, Nor a Spill Slot");
assert(MI->getOperand(2).isImm() && "Not an offset");
int Offset = MI->getOperand(2).getImm();
if (!TII->isValidOffset(Hexagon::L2_loadri_io, Offset)) {
@ -200,6 +193,6 @@ void llvm::initializeHexagonExpandPredSpillCodePass(PassRegistry &Registry) {
}
FunctionPass*
llvm::createHexagonExpandPredSpillCode(const HexagonTargetMachine &TM) {
return new HexagonExpandPredSpillCode(TM);
llvm::createHexagonExpandPredSpillCode() {
return new HexagonExpandPredSpillCode();
}

2
llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
View File

@ -160,7 +160,7 @@ void HexagonPassConfig::addPreEmitPass() {
addPass(createHexagonNewValueJump(), false);
// Expand Spill code for predicate registers.
addPass(createHexagonExpandPredSpillCode(TM), false);
addPass(createHexagonExpandPredSpillCode(), false);
// Split up TFRcondsets into conditional transfers.
addPass(createHexagonSplitTFRCondSets(TM), false);