forked from OSchip/llvm-project
AMDGPU/R600: Add MOV instructions to BFE patterns
R600 can't handle immediates for BFE, these will be eliminated later. Fixes powr/pow regressions n r600 since r334817 Differential Revision: https://reviews.llvm.org/D49641 llvm-svn: 338127
This commit is contained in:
Jan Vesely
parent
a703b8dc71
commit
6ff58ed5ca
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@ -753,30 +753,30 @@ multiclass BFEPattern <Instruction UBFE, Instruction SBFE, Instruction MOV> {
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// x & ((1 << y) - 1)
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def : AMDGPUPat <
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(and i32:$src, (add_oneuse (shl_oneuse 1, i32:$width), -1)),
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(UBFE $src, (i32 0), $width)
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(UBFE $src, (MOV (i32 0)), $width)
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>;
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// x & ~(-1 << y)
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def : AMDGPUPat <
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(and i32:$src, (xor_oneuse (shl_oneuse -1, i32:$width), -1)),
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(UBFE $src, (i32 0), $width)
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(UBFE $src, (MOV (i32 0)), $width)
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>;
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// x & (-1 >> (bitwidth - y))
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def : AMDGPUPat <
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(and i32:$src, (srl_oneuse -1, (sub 32, i32:$width))),
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(UBFE $src, (i32 0), $width)
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(UBFE $src, (MOV (i32 0)), $width)
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>;
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// x << (bitwidth - y) >> (bitwidth - y)
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def : AMDGPUPat <
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(srl (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)),
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(UBFE $src, (i32 0), $width)
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(UBFE $src, (MOV (i32 0)), $width)
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>;
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def : AMDGPUPat <
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(sra (shl_oneuse i32:$src, (sub 32, i32:$width)), (sub 32, i32:$width)),
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(SBFE $src, (i32 0), $width)
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(SBFE $src, (MOV (i32 0)), $width)
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>;
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}
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@ -0,0 +1,175 @@
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; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=EG %s
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; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cayman -verify-machineinstrs < %s | FileCheck -check-prefix=R600 -check-prefix=CM %s
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; Loosely based on test/CodeGen/{X86,AArch64}/extract-lowbits.ll,
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; but with all 64-bit tests, and tests with loads dropped.
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; Patterns:
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; a) x & (1 << nbits) - 1
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; b) x & ~(-1 << nbits)
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; c) x & (-1 >> (32 - y))
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; d) x << (32 - y) >> (32 - y)
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; are equivalent.
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; ---------------------------------------------------------------------------- ;
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; Pattern a. 32-bit
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; ---------------------------------------------------------------------------- ;
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; R600-LABEL: bzhi32_a0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
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; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
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define amdgpu_kernel void @bzhi32_a0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
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%onebit = shl i32 1, %numlowbits
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%mask = add nsw i32 %onebit, -1
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%masked = and i32 %mask, %val
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store i32 %masked, i32 addrspace(1)* %out
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ret void
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}
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; R600-LABEL: bzhi32_a1_indexzext:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
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; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
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define amdgpu_kernel void @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits, i32 addrspace(1)* %out) {
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%conv = zext i8 %numlowbits to i32
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%onebit = shl i32 1, %conv
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%mask = add nsw i32 %onebit, -1
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%masked = and i32 %mask, %val
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store i32 %masked, i32 addrspace(1)* %out
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ret void
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}
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; R600-LABEL: bzhi32_a4_commutative:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
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; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
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define amdgpu_kernel void @bzhi32_a4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
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%onebit = shl i32 1, %numlowbits
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%mask = add nsw i32 %onebit, -1
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%masked = and i32 %val, %mask ; swapped order
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store i32 %masked, i32 addrspace(1)* %out
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ret void
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}
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; ---------------------------------------------------------------------------- ;
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; Pattern b. 32-bit
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; ---------------------------------------------------------------------------- ;
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; R600-LABEL: bzhi32_b0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
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; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
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define amdgpu_kernel void @bzhi32_b0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
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%notmask = shl i32 -1, %numlowbits
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%mask = xor i32 %notmask, -1
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%masked = and i32 %mask, %val
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store i32 %masked, i32 addrspace(1)* %out
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ret void
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}
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; R600-LABEL: bzhi32_b1_indexzext:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
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; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
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define amdgpu_kernel void @bzhi32_b1_indexzext(i32 %val, i8 zeroext %numlowbits, i32 addrspace(1)* %out) {
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%conv = zext i8 %numlowbits to i32
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%notmask = shl i32 -1, %conv
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%mask = xor i32 %notmask, -1
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%masked = and i32 %mask, %val
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store i32 %masked, i32 addrspace(1)* %out
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ret void
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}
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; R600-LABEL: bzhi32_b4_commutative:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
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; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
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define amdgpu_kernel void @bzhi32_b4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
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%notmask = shl i32 -1, %numlowbits
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%mask = xor i32 %notmask, -1
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%masked = and i32 %val, %mask ; swapped order
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store i32 %masked, i32 addrspace(1)* %out
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ret void
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}
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; ---------------------------------------------------------------------------- ;
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; Pattern c. 32-bit
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; ---------------------------------------------------------------------------- ;
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; R600-LABEL: bzhi32_c0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
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; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
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define amdgpu_kernel void @bzhi32_c0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
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%numhighbits = sub i32 32, %numlowbits
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%mask = lshr i32 -1, %numhighbits
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%masked = and i32 %mask, %val
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store i32 %masked, i32 addrspace(1)* %out
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ret void
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}
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; R600-LABEL: bzhi32_c1_indexzext:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
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; R600: SUB_INT {{\*?}} [[SUBR:T[0-9]+]].[[SUBC:[XYZW]]], literal.x, KC0[2].Z
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; R600-NEXT: 32
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; R600-NEXT: AND_INT {{\*?}} {{T[0-9]+}}.[[AND1C:[XYZW]]], {{T[0-9]+|PV}}.[[SUBC]], literal.x
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; R600-NEXT: 255
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; R600: LSHR {{\*?}} {{T[0-9]}}.[[LSHRC:[XYZW]]], literal.x, {{T[0-9]+|PV}}.[[AND1C]]
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; R600-NEXT: -1
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; R600-NEXT: AND_INT {{[* ]*}}[[RET]], {{T[0-9]+|PV}}.[[LSHRC]], KC0[2].Y
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define amdgpu_kernel void @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits, i32 addrspace(1)* %out) {
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%numhighbits = sub i8 32, %numlowbits
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%sh_prom = zext i8 %numhighbits to i32
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%mask = lshr i32 -1, %sh_prom
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%masked = and i32 %mask, %val
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store i32 %masked, i32 addrspace(1)* %out
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ret void
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}
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; R600-LABEL: bzhi32_c4_commutative:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
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; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
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define amdgpu_kernel void @bzhi32_c4_commutative(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
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%numhighbits = sub i32 32, %numlowbits
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%mask = lshr i32 -1, %numhighbits
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%masked = and i32 %val, %mask ; swapped order
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store i32 %masked, i32 addrspace(1)* %out
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ret void
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}
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; ---------------------------------------------------------------------------- ;
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; Pattern d. 32-bit.
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; ---------------------------------------------------------------------------- ;
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; R600-LABEL: bzhi32_d0:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
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; R600: BFE_UINT {{\*?}} [[RET]], KC0[2].Y, 0.0, KC0[2].Z
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define amdgpu_kernel void @bzhi32_d0(i32 %val, i32 %numlowbits, i32 addrspace(1)* %out) {
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%numhighbits = sub i32 32, %numlowbits
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%highbitscleared = shl i32 %val, %numhighbits
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%masked = lshr i32 %highbitscleared, %numhighbits
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store i32 %masked, i32 addrspace(1)* %out
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ret void
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}
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; R600-LABEL: bzhi32_d1_indexzext:
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; EG: MEM_RAT_CACHELESS STORE_RAW [[RET:T[0-1]+\.[XYZW]]]
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; CM: MEM_RAT_CACHELESS STORE_DWORD [[RET:T[0-1]+\.[XYZW]]]
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; R600: SUB_INT {{\*?}} [[SUBR:T[0-9]+]].[[SUBC:[XYZW]]], literal.x, KC0[2].Z
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; R600-NEXT: 32
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; R600-NEXT: AND_INT {{\*?}} [[AND:T[0-9]+\.[XYZW]]], {{T[0-9]+|PV}}.[[SUBC]], literal.x
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; R600-NEXT: 255
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; R600: LSHL {{\*?}} {{T[0-9]}}.[[LSHLC:[XYZW]]], KC0[2].Y, {{T[0-9]+|PV}}.[[AND1C]]
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; R600: LSHR {{[* ]*}}[[RET]], {{T[0-9]+|PV}}.[[LSHLC]], [[AND]]
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define amdgpu_kernel void @bzhi32_d1_indexzext(i32 %val, i8 %numlowbits, i32 addrspace(1)* %out) {
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%numhighbits = sub i8 32, %numlowbits
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%sh_prom = zext i8 %numhighbits to i32
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%highbitscleared = shl i32 %val, %sh_prom
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%masked = lshr i32 %highbitscleared, %sh_prom
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store i32 %masked, i32 addrspace(1)* %out
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ret void
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}
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