forked from OSchip/llvm-project
AMDGPU: Fix assertion in performSHLPtrCombine for 64-bit pointers
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@ -8552,7 +8552,7 @@ SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
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EVT VT = N->getValueType(0);
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SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
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SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32);
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SDValue COffset = DAG.getConstant(Offset, SL, VT);
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SDNodeFlags Flags;
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Flags.setNoUnsignedWrap(N->getFlags().hasNoUnsignedWrap() &&
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@ -0,0 +1,21 @@
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
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; GCN-LABEL: {{^}}shl_base_global_ptr:
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; GCN: v_add_co_u32_e32 v[[EXTRA_LO:[0-9]+]], vcc, 0x80, v4
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; GCN: v_addc_co_u32_e32 v[[EXTRA_HI:[0-9]+]], vcc, 0, v5, vcc
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; GCN: v_lshlrev_b64 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, 2, v[4:5]
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; GCN: v_mov_b32_e32 [[THREE:v[0-9]+]], 3
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; GCN: global_atomic_and v{{\[}}[[LO]]:[[HI]]{{\]}}, [[THREE]], off offset:512
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; GCN: global_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[EXTRA_LO]]:[[EXTRA_HI]]{{\]}}
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define void @shl_base_global_ptr(i32 addrspace(1)* %out, i64 addrspace(1)* %extra.use, [512 x i32] addrspace(1)* %ptr) #0 {
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%arrayidx0 = getelementptr inbounds [512 x i32], [512 x i32] addrspace(1)* %ptr, i64 0, i64 32
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%cast = ptrtoint i32 addrspace(1)* %arrayidx0 to i64
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%shl = shl i64 %cast, 2
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%castback = inttoptr i64 %shl to i32 addrspace(1)*
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%val = atomicrmw and i32 addrspace(1)* %castback, i32 3 seq_cst
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store volatile i64 %cast, i64 addrspace(1)* %extra.use, align 4
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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