forked from OSchip/llvm-project
[X86] Replace __builtin_ia32_vbroadcastf128_pd256 and __builtin_ia32_vbroadcastf128_ps256 with an unaligned load intrinsics and a __builtin_shufflevector call.
llvm-svn: 333853
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@ -510,8 +510,6 @@ TARGET_BUILTIN(__builtin_ia32_movmskpd256, "iV4d", "nc", "avx")
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TARGET_BUILTIN(__builtin_ia32_movmskps256, "iV8f", "nc", "avx")
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TARGET_BUILTIN(__builtin_ia32_vzeroall, "v", "n", "avx")
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TARGET_BUILTIN(__builtin_ia32_vzeroupper, "v", "n", "avx")
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TARGET_BUILTIN(__builtin_ia32_vbroadcastf128_pd256, "V4dV2dC*", "n", "avx")
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TARGET_BUILTIN(__builtin_ia32_vbroadcastf128_ps256, "V8fV4fC*", "n", "avx")
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TARGET_BUILTIN(__builtin_ia32_lddqu256, "V32ccC*", "n", "avx")
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TARGET_BUILTIN(__builtin_ia32_maskloadpd, "V2dV2dC*V2LLi", "n", "avx")
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TARGET_BUILTIN(__builtin_ia32_maskloadps, "V4fV4fC*V4i", "n", "avx")
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@ -8300,26 +8300,6 @@ static Value *EmitX86MaskLogic(CodeGenFunction &CGF, Instruction::BinaryOps Opc,
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CGF.Builder.getIntNTy(std::max(NumElts, 8U)));
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}
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static Value *EmitX86SubVectorBroadcast(CodeGenFunction &CGF,
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ArrayRef<Value *> Ops,
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llvm::Type *DstTy,
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unsigned SrcSizeInBits,
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unsigned Align) {
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// Load the subvector.
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Value *SubVec = CGF.Builder.CreateAlignedLoad(Ops[0], Align);
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// Create broadcast mask.
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unsigned NumDstElts = DstTy->getVectorNumElements();
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unsigned NumSrcElts = SrcSizeInBits / DstTy->getScalarSizeInBits();
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SmallVector<uint32_t, 8> Mask;
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for (unsigned i = 0; i != NumDstElts; i += NumSrcElts)
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for (unsigned j = 0; j != NumSrcElts; ++j)
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Mask.push_back(j);
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return CGF.Builder.CreateShuffleVector(SubVec, SubVec, Mask, "subvecbcst");
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}
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static Value *EmitX86Select(CodeGenFunction &CGF,
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Value *Mask, Value *Op0, Value *Op1) {
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@ -8959,12 +8939,6 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
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case X86::BI__builtin_ia32_movdqa64load512_mask:
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return EmitX86MaskedLoad(*this, Ops, 64);
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case X86::BI__builtin_ia32_vbroadcastf128_pd256:
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case X86::BI__builtin_ia32_vbroadcastf128_ps256: {
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llvm::Type *DstTy = ConvertType(E->getType());
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return EmitX86SubVectorBroadcast(*this, Ops, DstTy, 128, 1);
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}
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case X86::BI__builtin_ia32_storehps:
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case X86::BI__builtin_ia32_storelps: {
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llvm::Type *PtrTy = llvm::PointerType::getUnqual(Int64Ty);
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@ -3111,7 +3111,9 @@ _mm256_broadcast_ss(float const *__a)
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static __inline __m256d __DEFAULT_FN_ATTRS
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_mm256_broadcast_pd(__m128d const *__a)
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{
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return (__m256d)__builtin_ia32_vbroadcastf128_pd256((__v2df const *)__a);
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__m128d __b = _mm_loadu_pd((const double *)__a);
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return (__m256d)__builtin_shufflevector((__v2df)__b, (__v2df)__b,
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0, 1, 0, 1);
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}
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/// Loads the data from a 128-bit vector of [4 x float] from the
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@ -3129,7 +3131,9 @@ _mm256_broadcast_pd(__m128d const *__a)
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static __inline __m256 __DEFAULT_FN_ATTRS
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_mm256_broadcast_ps(__m128 const *__a)
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{
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return (__m256)__builtin_ia32_vbroadcastf128_ps256((__v4sf const *)__a);
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__m128 __b = _mm_loadu_ps((const float *)__a);
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return (__m256)__builtin_shufflevector((__v4sf)__b, (__v4sf)__b,
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0, 1, 2, 3, 0, 1, 2, 3);
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}
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/* SIMD load ops */
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@ -466,8 +466,6 @@ void f0() {
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tmp_i = __builtin_ia32_movmskps256(tmp_V8f);
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__builtin_ia32_vzeroall();
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__builtin_ia32_vzeroupper();
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tmp_V4d = __builtin_ia32_vbroadcastf128_pd256(tmp_V2dCp);
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tmp_V8f = __builtin_ia32_vbroadcastf128_ps256(tmp_V4fCp);
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tmp_V32c = __builtin_ia32_lddqu256(tmp_cCp);
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tmp_V2d = __builtin_ia32_maskloadpd(tmp_V2dCp, tmp_V2LLi);
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tmp_V4f = __builtin_ia32_maskloadps(tmp_V4fCp, tmp_V4i);
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