forked from OSchip/llvm-project
AMDGPU/GlobalISel: Legalize GDS atomics
I noticed these don't use the _gfx9, non-m0 reading variants but not sure if that's a bug or not. It's the same in the DAG.
This commit is contained in:
Matt Arsenault
parent
5819159995
commit
6f961a1e7e
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@ -1196,14 +1196,15 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
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G_ATOMICRMW_MAX, G_ATOMICRMW_MIN, G_ATOMICRMW_UMAX,
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G_ATOMICRMW_UMIN})
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.legalFor({{S32, GlobalPtr}, {S32, LocalPtr},
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{S64, GlobalPtr}, {S64, LocalPtr}});
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{S64, GlobalPtr}, {S64, LocalPtr},
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{S32, RegionPtr}, {S64, RegionPtr}});
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if (ST.hasFlatAddressSpace()) {
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Atomics.legalFor({{S32, FlatPtr}, {S64, FlatPtr}});
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}
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if (ST.hasLDSFPAtomics()) {
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getActionDefinitionsBuilder(G_ATOMICRMW_FADD)
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.legalFor({{S32, LocalPtr}});
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.legalFor({{S32, LocalPtr}, {S32, RegionPtr}});
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}
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// BUFFER/FLAT_ATOMIC_CMP_SWAP on GCN GPUs needs input marshalling, and output
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@ -0,0 +1,173 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
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---
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name: atomic_cmpxchg_s32_region
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX6-LABEL: name: atomic_cmpxchg_s32_region
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; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: [[DS_CMPST_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_CMPST_RTN_B32 [[COPY]], [[COPY1]], [[COPY2]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
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; GFX6: $vgpr0 = COPY [[DS_CMPST_RTN_B32_]]
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; GFX7-LABEL: name: atomic_cmpxchg_s32_region
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; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX7: $m0 = S_MOV_B32 -1
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; GFX7: [[DS_CMPST_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_CMPST_RTN_B32 [[COPY]], [[COPY1]], [[COPY2]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
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; GFX7: $vgpr0 = COPY [[DS_CMPST_RTN_B32_]]
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; GFX9-LABEL: name: atomic_cmpxchg_s32_region
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; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX9: [[DS_CMPST_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_CMPST_RTN_B32 [[COPY]], [[COPY1]], [[COPY2]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
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; GFX9: $vgpr0 = COPY [[DS_CMPST_RTN_B32_]]
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%0:vgpr(p2) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = COPY $vgpr2
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%3:vgpr(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst 4, addrspace 2)
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$vgpr0 = COPY %3
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...
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---
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name: atomic_cmpxchg_s32_region_gep4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX6-LABEL: name: atomic_cmpxchg_s32_region_gep4
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; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX6: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
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; GFX6: %4:vgpr_32, dead %6:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: [[DS_CMPST_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_CMPST_RTN_B32 %4, [[COPY1]], [[COPY2]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
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; GFX6: $vgpr0 = COPY [[DS_CMPST_RTN_B32_]]
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; GFX7-LABEL: name: atomic_cmpxchg_s32_region_gep4
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; GFX7: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX7: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX7: $m0 = S_MOV_B32 -1
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; GFX7: [[DS_CMPST_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_CMPST_RTN_B32 [[COPY]], [[COPY1]], [[COPY2]], 4, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
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; GFX7: $vgpr0 = COPY [[DS_CMPST_RTN_B32_]]
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; GFX9-LABEL: name: atomic_cmpxchg_s32_region_gep4
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; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX9: [[DS_CMPST_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_CMPST_RTN_B32 [[COPY]], [[COPY1]], [[COPY2]], 4, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
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; GFX9: $vgpr0 = COPY [[DS_CMPST_RTN_B32_]]
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%0:vgpr(p2) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = COPY $vgpr2
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%3:vgpr(s32) = G_CONSTANT i32 4
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%4:vgpr(p2) = G_PTR_ADD %0, %3
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%5:vgpr(s32) = G_ATOMIC_CMPXCHG %4, %1, %2 :: (load store seq_cst 4, addrspace 2)
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$vgpr0 = COPY %5
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...
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---
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name: atomic_cmpxchg_s64_region
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
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; GFX6-LABEL: name: atomic_cmpxchg_s64_region
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; GFX6: liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
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; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: [[DS_CMPST_RTN_B64_:%[0-9]+]]:vreg_64 = DS_CMPST_RTN_B64 [[COPY]], [[COPY1]], [[COPY2]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 8, addrspace 2)
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; GFX6: $vgpr0_vgpr1 = COPY [[DS_CMPST_RTN_B64_]]
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; GFX7-LABEL: name: atomic_cmpxchg_s64_region
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; GFX7: liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
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; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX7: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
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; GFX7: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
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; GFX7: $m0 = S_MOV_B32 -1
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; GFX7: [[DS_CMPST_RTN_B64_:%[0-9]+]]:vreg_64 = DS_CMPST_RTN_B64 [[COPY]], [[COPY1]], [[COPY2]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 8, addrspace 2)
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; GFX7: $vgpr0_vgpr1 = COPY [[DS_CMPST_RTN_B64_]]
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; GFX9-LABEL: name: atomic_cmpxchg_s64_region
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; GFX9: liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
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; GFX9: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
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; GFX9: [[DS_CMPST_RTN_B64_:%[0-9]+]]:vreg_64 = DS_CMPST_RTN_B64 [[COPY]], [[COPY1]], [[COPY2]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 8, addrspace 2)
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; GFX9: $vgpr0_vgpr1 = COPY [[DS_CMPST_RTN_B64_]]
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%0:vgpr(p2) = COPY $vgpr0
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%1:vgpr(s64) = COPY $vgpr1_vgpr2
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%2:vgpr(s64) = COPY $vgpr3_vgpr4
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%3:vgpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst 8, addrspace 2)
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$vgpr0_vgpr1 = COPY %3
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...
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---
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name: atomic_cmpxchg_s64_region_gep4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
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; GFX6-LABEL: name: atomic_cmpxchg_s64_region_gep4
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; GFX6: liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
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; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
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; GFX6: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: [[DS_CMPST_RTN_B64_:%[0-9]+]]:vreg_64 = DS_CMPST_RTN_B64 [[COPY]], [[COPY1]], [[COPY2]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 8, addrspace 2)
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; GFX6: $vgpr0_vgpr1 = COPY [[DS_CMPST_RTN_B64_]]
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; GFX7-LABEL: name: atomic_cmpxchg_s64_region_gep4
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; GFX7: liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
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; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX7: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
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; GFX7: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
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; GFX7: $m0 = S_MOV_B32 -1
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; GFX7: [[DS_CMPST_RTN_B64_:%[0-9]+]]:vreg_64 = DS_CMPST_RTN_B64 [[COPY]], [[COPY1]], [[COPY2]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 8, addrspace 2)
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; GFX7: $vgpr0_vgpr1 = COPY [[DS_CMPST_RTN_B64_]]
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; GFX9-LABEL: name: atomic_cmpxchg_s64_region_gep4
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; GFX9: liveins: $vgpr0, $vgpr1_vgpr2, $vgpr3_vgpr4
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2
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; GFX9: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
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; GFX9: [[DS_CMPST_RTN_B64_:%[0-9]+]]:vreg_64 = DS_CMPST_RTN_B64 [[COPY]], [[COPY1]], [[COPY2]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 8, addrspace 2)
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; GFX9: $vgpr0_vgpr1 = COPY [[DS_CMPST_RTN_B64_]]
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%0:vgpr(p2) = COPY $vgpr0
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%1:vgpr(s64) = COPY $vgpr1_vgpr2
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%2:vgpr(s64) = COPY $vgpr3_vgpr4
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%3:vgpr(s32) = G_CONSTANT i32 4
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%4:vgpr(p2) = G_PTR_ADD %0, %3
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%5:vgpr(s64) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst 8, addrspace 2)
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$vgpr0_vgpr1 = COPY %5
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...
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@ -0,0 +1,116 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX8 %s
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
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# GFX6/7 selection should fail.
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -disable-gisel-legality-check -o - %s | FileCheck -check-prefix=GFX6 %s
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# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -disable-gisel-legality-check -o - %s | FileCheck -check-prefix=GFX6 %s
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---
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name: atomicrmw_fadd_s32_region
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX8-LABEL: name: atomicrmw_fadd_s32_region
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; GFX8: liveins: $vgpr0, $vgpr1
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8: $m0 = S_MOV_B32 -1
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; GFX8: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
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; GFX8: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
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; GFX9-LABEL: name: atomicrmw_fadd_s32_region
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; GFX9: liveins: $vgpr0, $vgpr1
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; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
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; GFX9: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
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; GFX6-LABEL: name: atomicrmw_fadd_s32_region
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; GFX6: liveins: $vgpr0, $vgpr1
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; GFX6: [[COPY:%[0-9]+]]:vgpr(p2) = COPY $vgpr0
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; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; GFX6: $m0 = S_MOV_B32 -1
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; GFX6: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr_32(s32) = G_ATOMICRMW_FADD [[COPY]](p2), [[COPY1]] :: (load store seq_cst 4, addrspace 2)
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; GFX6: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)
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%0:vgpr(p2) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_ATOMICRMW_FADD %0(p2), %1 :: (load store seq_cst 4, addrspace 2)
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$vgpr0 = COPY %2
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...
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---
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name: atomicrmw_fadd_s32_region_noret
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GFX8-LABEL: name: atomicrmw_fadd_s32_region_noret
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; GFX8: liveins: $vgpr0, $vgpr1
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; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX8: $m0 = S_MOV_B32 -1
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; GFX8: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
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; GFX9-LABEL: name: atomicrmw_fadd_s32_region_noret
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; GFX9: liveins: $vgpr0, $vgpr1
|
||||
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GFX9: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
|
||||
; GFX6-LABEL: name: atomicrmw_fadd_s32_region_noret
|
||||
; GFX6: liveins: $vgpr0, $vgpr1
|
||||
; GFX6: [[COPY:%[0-9]+]]:vgpr(p2) = COPY $vgpr0
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; GFX6: $m0 = S_MOV_B32 -1
|
||||
; GFX6: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr(s32) = G_ATOMICRMW_FADD [[COPY]](p2), [[COPY1]] :: (load store seq_cst 4, addrspace 2)
|
||||
%0:vgpr(p2) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s32) = G_ATOMICRMW_FADD %0(p2), %1 :: (load store seq_cst 4, addrspace 2)
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: atomicrmw_fadd_s32_region_gep4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
; GFX8-LABEL: name: atomicrmw_fadd_s32_region_gep4
|
||||
; GFX8: liveins: $vgpr0, $vgpr1
|
||||
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GFX8: $m0 = S_MOV_B32 -1
|
||||
; GFX8: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 4, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
|
||||
; GFX8: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
|
||||
; GFX9-LABEL: name: atomicrmw_fadd_s32_region_gep4
|
||||
; GFX9: liveins: $vgpr0, $vgpr1
|
||||
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GFX9: [[DS_ADD_RTN_F32_:%[0-9]+]]:vgpr_32 = DS_ADD_RTN_F32 [[COPY]], [[COPY1]], 4, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
|
||||
; GFX9: $vgpr0 = COPY [[DS_ADD_RTN_F32_]]
|
||||
; GFX6-LABEL: name: atomicrmw_fadd_s32_region_gep4
|
||||
; GFX6: liveins: $vgpr0, $vgpr1
|
||||
; GFX6: [[COPY:%[0-9]+]]:vgpr(p2) = COPY $vgpr0
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; GFX6: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 4
|
||||
; GFX6: [[PTR_ADD:%[0-9]+]]:vgpr(p2) = G_PTR_ADD [[COPY]], [[C]](s32)
|
||||
; GFX6: $m0 = S_MOV_B32 -1
|
||||
; GFX6: [[ATOMICRMW_FADD:%[0-9]+]]:vgpr_32(s32) = G_ATOMICRMW_FADD [[PTR_ADD]](p2), [[COPY1]] :: (load store seq_cst 4, addrspace 2)
|
||||
; GFX6: $vgpr0 = COPY [[ATOMICRMW_FADD]](s32)
|
||||
%0:vgpr(p2) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s32) = G_CONSTANT i32 4
|
||||
%3:vgpr(p2) = G_PTR_ADD %0, %2
|
||||
%4:vgpr(s32) = G_ATOMICRMW_FADD %3(p2), %1 :: (load store seq_cst 4, addrspace 2)
|
||||
$vgpr0 = COPY %4
|
||||
|
||||
...
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX6 %s
|
||||
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
|
||||
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX7 %s
|
||||
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
|
||||
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=GFX9 %s
|
||||
|
||||
|
||||
---
|
||||
name: atomicrmw_xchg_s32_region
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
; GFX6-LABEL: name: atomicrmw_xchg_s32_region
|
||||
; GFX6: liveins: $vgpr0, $vgpr1
|
||||
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GFX6: $m0 = S_MOV_B32 -1
|
||||
; GFX6: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
|
||||
; GFX6: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
|
||||
; GFX7-LABEL: name: atomicrmw_xchg_s32_region
|
||||
; GFX7: liveins: $vgpr0, $vgpr1
|
||||
; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GFX7: $m0 = S_MOV_B32 -1
|
||||
; GFX7: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
|
||||
; GFX7: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
|
||||
; GFX9-LABEL: name: atomicrmw_xchg_s32_region
|
||||
; GFX9: liveins: $vgpr0, $vgpr1
|
||||
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GFX9: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
|
||||
; GFX9: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
|
||||
%0:vgpr(p2) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s32) = G_ATOMICRMW_XCHG %0(p2), %1 :: (load store seq_cst 4, addrspace 2)
|
||||
$vgpr0 = COPY %2
|
||||
|
||||
...
|
||||
|
||||
---
|
||||
name: atomicrmw_xchg_s32_region_gep4
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
tracksRegLiveness: true
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
|
||||
; GFX6-LABEL: name: atomicrmw_xchg_s32_region_gep4
|
||||
; GFX6: liveins: $vgpr0, $vgpr1
|
||||
; GFX6: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GFX6: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GFX6: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 4, implicit $exec
|
||||
; GFX6: %3:vgpr_32, dead %5:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[V_MOV_B32_e32_]], 0, implicit $exec
|
||||
; GFX6: $m0 = S_MOV_B32 -1
|
||||
; GFX6: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 %3, [[COPY1]], 0, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
|
||||
; GFX6: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
|
||||
; GFX7-LABEL: name: atomicrmw_xchg_s32_region_gep4
|
||||
; GFX7: liveins: $vgpr0, $vgpr1
|
||||
; GFX7: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GFX7: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GFX7: $m0 = S_MOV_B32 -1
|
||||
; GFX7: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 4, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
|
||||
; GFX7: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
|
||||
; GFX9-LABEL: name: atomicrmw_xchg_s32_region_gep4
|
||||
; GFX9: liveins: $vgpr0, $vgpr1
|
||||
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; GFX9: [[DS_WRXCHG_RTN_B32_:%[0-9]+]]:vgpr_32 = DS_WRXCHG_RTN_B32 [[COPY]], [[COPY1]], 4, 1, implicit $m0, implicit $exec :: (load store seq_cst 4, addrspace 2)
|
||||
; GFX9: $vgpr0 = COPY [[DS_WRXCHG_RTN_B32_]]
|
||||
%0:vgpr(p2) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s32) = G_CONSTANT i32 4
|
||||
%3:vgpr(p2) = G_PTR_ADD %0, %2
|
||||
%4:vgpr(s32) = G_ATOMICRMW_XCHG %3(p2), %1 :: (load store seq_cst 4, addrspace 2)
|
||||
$vgpr0 = COPY %4
|
||||
|
||||
...
|
||||
Loading…
Reference in New Issue