From 6f778fed8e50a00a08297705148774b67a9da9c8 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Tue, 15 Jun 2021 13:15:42 +0100 Subject: [PATCH] [AMDGPU] Set more flags on Real instructions This does not affect codegen, which only tests these flags on Pseudo instructions, but might help llvm-mca which has to work with Real instructions. In particular setting LGKM_CNT on DS instructions helps with the problem identified in D104149. Differential Revision: https://reviews.llvm.org/D104293 --- llvm/lib/Target/AMDGPU/BUFInstructions.td | 8 ++++++++ llvm/lib/Target/AMDGPU/DSInstructions.td | 1 + llvm/lib/Target/AMDGPU/FLATInstructions.td | 4 ++++ llvm/lib/Target/AMDGPU/SMInstructions.td | 16 +++++++--------- 4 files changed, 20 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td index 6ec17bc7f3fd..94bf79e3aa88 100644 --- a/llvm/lib/Target/AMDGPU/BUFInstructions.td +++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td @@ -110,6 +110,10 @@ class MTBUF_Real : let isPseudo = 0; let isCodeGenOnly = 0; + let VM_CNT = 1; + let EXP_CNT = 1; + let MTBUF = 1; + // copy relevant pseudo op flags let UseNamedOperandTable = ps.UseNamedOperandTable; let SubtargetPredicate = ps.SubtargetPredicate; @@ -341,6 +345,10 @@ class MUBUF_Real : let isPseudo = 0; let isCodeGenOnly = 0; + let VM_CNT = 1; + let EXP_CNT = 1; + let MUBUF = 1; + // copy relevant pseudo op flags let SubtargetPredicate = ps.SubtargetPredicate; let AsmMatchConverter = ps.AsmMatchConverter; diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td index 9b15a1a2d5ee..53ff88d44f5b 100644 --- a/llvm/lib/Target/AMDGPU/DSInstructions.td +++ b/llvm/lib/Target/AMDGPU/DSInstructions.td @@ -58,6 +58,7 @@ class DS_Real : let isPseudo = 0; let isCodeGenOnly = 0; + let LGKM_CNT = 1; let DS = 1; let UseNamedOperandTable = 1; diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td index 74a9db0f1c4b..556eb12c4ec6 100644 --- a/llvm/lib/Target/AMDGPU/FLATInstructions.td +++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td @@ -81,6 +81,8 @@ class FLAT_Real op, FLAT_Pseudo ps> : let isPseudo = 0; let isCodeGenOnly = 0; + let FLAT = 1; + // copy relevant pseudo op flags let SubtargetPredicate = ps.SubtargetPredicate; let AsmMatchConverter = ps.AsmMatchConverter; @@ -88,6 +90,8 @@ class FLAT_Real op, FLAT_Pseudo ps> : let TSFlags = ps.TSFlags; let UseNamedOperandTable = ps.UseNamedOperandTable; let SchedRW = ps.SchedRW; + let VM_CNT = ps.VM_CNT; + let LGKM_CNT = ps.LGKM_CNT; // encoding fields bits<8> vaddr; diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td index 3ecbdf519960..88a806f18fc4 100644 --- a/llvm/lib/Target/AMDGPU/SMInstructions.td +++ b/llvm/lib/Target/AMDGPU/SMInstructions.td @@ -57,11 +57,15 @@ class SM_Real Instruction Opcode = !cast(NAME); // copy relevant pseudo op flags + let LGKM_CNT = ps.LGKM_CNT; + let SMRD = ps.SMRD; + let mayStore = ps.mayStore; + let mayLoad = ps.mayLoad; + let hasSideEffects = ps.hasSideEffects; + let UseNamedOperandTable = ps.UseNamedOperandTable; + let SchedRW = ps.SchedRW; let SubtargetPredicate = ps.SubtargetPredicate; let AsmMatchConverter = ps.AsmMatchConverter; - let UseNamedOperandTable = ps.UseNamedOperandTable; - let SMRD = ps.SMRD; - let SchedRW = ps.SchedRW; let TSFlags = ps.TSFlags; @@ -700,12 +704,6 @@ class SMRD_Real_Load_IMM_ci op, SM_Load_Pseudo ps> : let DecoderNamespace = "GFX7"; let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, CPol:$cpol); - let LGKM_CNT = ps.LGKM_CNT; - let mayLoad = ps.mayLoad; - let mayStore = ps.mayStore; - let hasSideEffects = ps.hasSideEffects; - let SchedRW = ps.SchedRW; - let Inst{7-0} = 0xff; let Inst{8} = 0; let Inst{14-9} = sbase{6-1};