forked from OSchip/llvm-project
The generic DAG combiner can now fold atomic fences when needed, so switch
to using that. llvm-svn: 106633
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@ -347,6 +347,12 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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if (!Subtarget->hasSSE2())
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setOperationAction(ISD::MEMBARRIER , MVT::Other, Expand);
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// On X86 and X86-64, atomic operations are lowered to locked instructions.
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// Locked instructions, in turn, have implicit fence semantics (all memory
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// operations are flushed before issuing the locked instruction, and they
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// are not buffered), so we can fold away the common pattern of
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// fence-atomic-fence.
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setShouldFoldAtomicFences(true);
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// Expand certain atomics
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setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i8, Custom);
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@ -1012,7 +1018,6 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setTargetDAGCombine(ISD::SRL);
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::STORE);
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setTargetDAGCombine(ISD::MEMBARRIER);
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setTargetDAGCombine(ISD::ZERO_EXTEND);
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if (Subtarget->is64Bit())
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setTargetDAGCombine(ISD::MUL);
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@ -9821,61 +9826,6 @@ static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) {
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return SDValue();
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}
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// On X86 and X86-64, atomic operations are lowered to locked instructions.
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// Locked instructions, in turn, have implicit fence semantics (all memory
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// operations are flushed before issuing the locked instruction, and they
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// are not buffered), so we can fold away the common pattern of
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// fence-atomic-fence.
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static SDValue PerformMEMBARRIERCombine(SDNode* N, SelectionDAG &DAG) {
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SDValue atomic = N->getOperand(0);
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switch (atomic.getOpcode()) {
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case ISD::ATOMIC_CMP_SWAP:
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case ISD::ATOMIC_SWAP:
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case ISD::ATOMIC_LOAD_ADD:
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case ISD::ATOMIC_LOAD_SUB:
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case ISD::ATOMIC_LOAD_AND:
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case ISD::ATOMIC_LOAD_OR:
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case ISD::ATOMIC_LOAD_XOR:
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case ISD::ATOMIC_LOAD_NAND:
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case ISD::ATOMIC_LOAD_MIN:
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case ISD::ATOMIC_LOAD_MAX:
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case ISD::ATOMIC_LOAD_UMIN:
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case ISD::ATOMIC_LOAD_UMAX:
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break;
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default:
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return SDValue();
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}
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SDValue fence = atomic.getOperand(0);
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if (fence.getOpcode() != ISD::MEMBARRIER)
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return SDValue();
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switch (atomic.getOpcode()) {
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case ISD::ATOMIC_CMP_SWAP:
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return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
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fence.getOperand(0),
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atomic.getOperand(1), atomic.getOperand(2),
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atomic.getOperand(3)), atomic.getResNo());
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case ISD::ATOMIC_SWAP:
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case ISD::ATOMIC_LOAD_ADD:
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case ISD::ATOMIC_LOAD_SUB:
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case ISD::ATOMIC_LOAD_AND:
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case ISD::ATOMIC_LOAD_OR:
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case ISD::ATOMIC_LOAD_XOR:
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case ISD::ATOMIC_LOAD_NAND:
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case ISD::ATOMIC_LOAD_MIN:
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case ISD::ATOMIC_LOAD_MAX:
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case ISD::ATOMIC_LOAD_UMIN:
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case ISD::ATOMIC_LOAD_UMAX:
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return SDValue(DAG.UpdateNodeOperands(atomic.getNode(),
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fence.getOperand(0),
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atomic.getOperand(1), atomic.getOperand(2)),
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atomic.getResNo());
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default:
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return SDValue();
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}
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}
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static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) {
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// (i32 zext (and (i8 x86isd::setcc_carry), 1)) ->
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// (and (i32 x86isd::setcc_carry), 1)
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@ -9923,7 +9873,6 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::FAND: return PerformFANDCombine(N, DAG);
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case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
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case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG);
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case ISD::MEMBARRIER: return PerformMEMBARRIERCombine(N, DAG);
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case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG);
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}
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