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[ARM] Add enhanced counter virtualization system registers 

Summary:
This patch upstreams support for the ARMv8.6A Enhanced Counter Virtualization
(ECV) extension, which adds 6 new system registers.

See ARMv8.6-ECV in the Arm Architecture Reference Manual Armv8 for more
information.

Reviewers: t.p.northover, rengolin, SjoerdMeijer, pcc, ab, chill

Reviewed By: SjoerdMeijer

Subscribers: LukeGeeson, ostannard, kristof.beyls, hiraditya, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77094
This commit is contained in:
Oliver Stannard 2020-04-05 14:49:49 +01:00 committed by Ties Stuij
parent 3f9cdd44d7
commit 6f60eb4a3c
5 changed files with 102 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
llvm/lib/Target/AArch64/AArch64.td
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@ -376,6 +376,10 @@ def FeatureBF16 : SubtargetFeature<"bf16", "HasBF16",
def FeatureFineGrainedTraps : SubtargetFeature<"fgt", "HasFineGrainedTraps",
"true", "Enable fine grained virtualization traps extension">;
def FeatureEnhancedCounterVirtualization :
SubtargetFeature<"ecv", "HasEnhancedCounterVirtualization",
"true", "Enable enhanced counter virtualization extension">;
//===----------------------------------------------------------------------===//
// Architectures.
@ -408,7 +412,8 @@ def HasV8_5aOps : SubtargetFeature<
def HasV8_6aOps : SubtargetFeature<
"v8.6a", "HasV8_6aOps", "true", "Support ARM v8.6a instructions",
[HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps]>;
[HasV8_5aOps, FeatureAMVS, FeatureBF16, FeatureFineGrainedTraps,
FeatureEnhancedCounterVirtualization]>;
//===----------------------------------------------------------------------===//
// Register File Description

4
llvm/lib/Target/AArch64/AArch64Subtarget.h
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@ -149,6 +149,7 @@ protected:
bool HasBF16 = false;
bool HasAMVS = false;
bool HasFineGrainedTraps = false;
bool HasEnhancedCounterVirtualization = false;
// Arm SVE2 extensions
bool HasSVE2AES = false;
@ -417,6 +418,9 @@ public:
// Armv8.6-A Extensions
bool hasBF16() const { return HasBF16; }
bool hasFineGrainedTraps() const { return HasFineGrainedTraps; }
bool hasEnhancedCounterVirtualization() const {
return HasEnhancedCounterVirtualization;
}
bool isLittleEndian() const { return IsLittle; }

11
llvm/lib/Target/AArch64/AArch64SystemOperands.td
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@ -1512,6 +1512,17 @@ def : RWSysReg<"HDFGRTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b100>;
def : RWSysReg<"HDFGWTR_EL2", 0b11, 0b100, 0b0011, 0b0001, 0b101>;
}
// v8.6a Enhanced Counter Virtualization
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureEnhancedCounterVirtualization} }] in {
def : RWSysReg<"CNTSCALE_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b100>;
def : RWSysReg<"CNTISCALE_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b101>;
def : RWSysReg<"CNTPOFF_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b110>;
def : RWSysReg<"CNTVFRQ_EL2", 0b11, 0b100, 0b1110, 0b0000, 0b111>;
def : RWSysReg<"CNTPCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b101>;
def : RWSysReg<"CNTVCTSS_EL0", 0b11, 0b011, 0b1110, 0b0000, 0b110>;
}
// Cyclone specific system registers
// Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::ProcAppleA7} }] in

41
llvm/test/MC/AArch64/armv8.6a-ecv.s Normal file
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@ -0,0 +1,41 @@
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+ecv < %s | FileCheck %s
// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+v8.6a < %s | FileCheck %s
// RUN: not llvm-mc -triple aarch64 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=NOECV
msr CNTSCALE_EL2, x1
msr CNTISCALE_EL2, x11
msr CNTPOFF_EL2, x22
msr CNTVFRQ_EL2, x3
msr CNTPCTSS_EL0, x13
msr CNTVCTSS_EL0, x23
// CHECK: msr CNTSCALE_EL2, x1 // encoding: [0x81,0xe0,0x1c,0xd5]
// CHECK: msr CNTISCALE_EL2, x11 // encoding: [0xab,0xe0,0x1c,0xd5]
// CHECK: msr CNTPOFF_EL2, x22 // encoding: [0xd6,0xe0,0x1c,0xd5]
// CHECK: msr CNTVFRQ_EL2, x3 // encoding: [0xe3,0xe0,0x1c,0xd5]
// CHECK: msr CNTPCTSS_EL0, x13 // encoding: [0xad,0xe0,0x1b,0xd5]
// CHECK: msr CNTVCTSS_EL0, x23 // encoding: [0xd7,0xe0,0x1b,0xd5]
// NOECV :error: expected writable system register or pstate
// NOECV: error: expected writable system register or pstate
// NOECV: error: expected writable system register or pstate
// NOECV: error: expected writable system register or pstate
// NOECV: error: expected writable system register or pstate
// NOECV: error: expected writable system register or pstate
mrs x0, CNTSCALE_EL2
mrs x5, CNTISCALE_EL2
mrs x10, CNTPOFF_EL2
mrs x15, CNTVFRQ_EL2
mrs x20, CNTPCTSS_EL0
mrs x30, CNTVCTSS_EL0
// CHECK: mrs x0, CNTSCALE_EL2 // encoding: [0x80,0xe0,0x3c,0xd5]
// CHECK: mrs x5, CNTISCALE_EL2 // encoding: [0xa5,0xe0,0x3c,0xd5]
// CHECK: mrs x10, CNTPOFF_EL2 // encoding: [0xca,0xe0,0x3c,0xd5]
// CHECK: mrs x15, CNTVFRQ_EL2 // encoding: [0xef,0xe0,0x3c,0xd5]
// CHECK: mrs x20, CNTPCTSS_EL0 // encoding: [0xb4,0xe0,0x3b,0xd5]
// CHECK: mrs x30, CNTVCTSS_EL0 // encoding: [0xde,0xe0,0x3b,0xd5]
// NOECV: error: expected readable system register
// NOECV: error: expected readable system register
// NOECV: error: expected readable system register
// NOECV: error: expected readable system register
// NOECV: error: expected readable system register
// NOECV: error: expected readable system register

40
llvm/test/MC/Disassembler/AArch64/armv8.6a-ecv.txt Normal file
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@ -0,0 +1,40 @@
# RUN: llvm-mc -triple=aarch64 -mattr=+ecv -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOFGT
[0x81,0xe0,0x1c,0xd5]
[0xab,0xe0,0x1c,0xd5]
[0xd6,0xe0,0x1c,0xd5]
[0xe3,0xe0,0x1c,0xd5]
[0xad,0xe0,0x1b,0xd5]
[0xd7,0xe0,0x1b,0xd5]
# CHECK: msr CNTSCALE_EL2, x1
# CHECK: msr CNTISCALE_EL2, x11
# CHECK: msr CNTPOFF_EL2, x22
# CHECK: msr CNTVFRQ_EL2, x3
# CHECK: msr CNTPCTSS_EL0, x13
# CHECK: msr CNTVCTSS_EL0, x23
# NOFGT: msr S3_4_C14_C0_4, x1
# NOFGT: msr S3_4_C14_C0_5, x11
# NOFGT: msr S3_4_C14_C0_6, x22
# NOFGT: msr S3_4_C14_C0_7, x3
# NOFGT: msr S3_3_C14_C0_5, x13
# NOFGT: msr S3_3_C14_C0_6, x23
[0x80,0xe0,0x3c,0xd5]
[0xa5,0xe0,0x3c,0xd5]
[0xca,0xe0,0x3c,0xd5]
[0xef,0xe0,0x3c,0xd5]
[0xb4,0xe0,0x3b,0xd5]
[0xde,0xe0,0x3b,0xd5]
# CHECK: mrs x0, CNTSCALE_EL2
# CHECK: mrs x5, CNTISCALE_EL2
# CHECK: mrs x10, CNTPOFF_EL2
# CHECK: mrs x15, CNTVFRQ_EL2
# CHECK: mrs x20, CNTPCTSS_EL0
# CHECK: mrs x30, CNTVCTSS_EL0
# NOFGT: mrs x0, S3_4_C14_C0_4
# NOFGT: mrs x5, S3_4_C14_C0_5
# NOFGT: mrs x10, S3_4_C14_C0_6
# NOFGT: mrs x15, S3_4_C14_C0_7
# NOFGT: mrs x20, S3_3_C14_C0_5
# NOFGT: mrs x30, S3_3_C14_C0_6