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[PowerPC] Add Set Boolean Condition Instruction Definitions and MC Tests 

This patch adds the instruction definitions and assembly/disassembly tests for
the set boolean condition instructions. This also includes the negative, and
reverse variants of the instruction.

Differential Revision: https://reviews.llvm.org/D86252
This commit is contained in:
Amy Kwan 2020-09-17 18:20:37 -05:00
parent 2c3bc918db
commit 6f3c0991bf
3 changed files with 51 additions and 0 deletions
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27
llvm/lib/Target/PowerPC/PPCInstrPrefix.td
View File

@ -481,6 +481,13 @@ class XX2_BF3_XO5_XB6_XO9<bits<6> opcode, bits<5> xo2, bits<9> xo, dag OOL,
let Inst{31} = 0;
}
// X-Form: [ PO RT BI /// XO / ]
class XForm_XT5_BI5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmstr, InstrItinClass itin, list<dag> pattern>
: XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
let B = 0;
}
multiclass MLS_DForm_R_SI34_RTA5_MEM_p<bits<6> opcode, dag OOL, dag IOL,
dag PCRel_IOL, string asmstr,
InstrItinClass itin> {
@ -877,6 +884,26 @@ let Predicates = [PrefixInstrs] in {
}
let Predicates = [IsISA3_1] in {
def SETBC : XForm_XT5_BI5<31, 384, (outs gprc:$RT), (ins crbitrc:$BI),
"setbc $RT, $BI", IIC_IntCompare, []>;
def SETBCR : XForm_XT5_BI5<31, 416, (outs gprc:$RT), (ins crbitrc:$BI),
"setbcr $RT, $BI", IIC_IntCompare, []>;
def SETNBC : XForm_XT5_BI5<31, 448, (outs gprc:$RT), (ins crbitrc:$BI),
"setnbc $RT, $BI", IIC_IntCompare, []>;
def SETNBCR : XForm_XT5_BI5<31, 480, (outs gprc:$RT), (ins crbitrc:$BI),
"setnbcr $RT, $BI", IIC_IntCompare, []>;
let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
def SETBC8 : XForm_XT5_BI5<31, 384, (outs g8rc:$RT), (ins crbitrc:$BI),
"setbc $RT, $BI", IIC_IntCompare, []>;
def SETBCR8 : XForm_XT5_BI5<31, 416, (outs g8rc:$RT), (ins crbitrc:$BI),
"setbcr $RT, $BI", IIC_IntCompare, []>;
def SETNBC8 : XForm_XT5_BI5<31, 448, (outs g8rc:$RT), (ins crbitrc:$BI),
"setnbc $RT, $BI", IIC_IntCompare, []>;
def SETNBCR8 : XForm_XT5_BI5<31, 480, (outs g8rc:$RT), (ins crbitrc:$BI),
"setnbcr $RT, $BI", IIC_IntCompare, []>;
}
def VSLDBI : VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT),
(ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
"vsldbi $VRT, $VRA, $VRB, $SH",

12
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-ISA31.txt
View File

@ -225,6 +225,18 @@
# CHECK: xxblendvd 6, 63, 21, 34
0x05 0x00 0x00 0x00 0x84 0xdf 0xa8 0xbc
# CHECK: setbc 21, 11
0x7e 0xab 0x03 0x00
# CHECK: setbcr 21, 11
0x7e 0xab 0x03 0x40
# CHECK: setnbc 21, 11
0x7e 0xab 0x03 0x80
# CHECK: setnbcr 21, 11
0x7e 0xab 0x03 0xc0
# CHECK: vsldbi 2, 3, 4, 5
0x10 0x43 0x21 0x56

12
llvm/test/MC/PowerPC/ppc64-encoding-ISA31.s
View File

@ -351,6 +351,18 @@
# CHECK-LE: xxblendvd 6, 63, 21, 34 # encoding: [0x00,0x00,0x00,0x05,
# CHECK-LE-SAME: 0xbc,0xa8,0xdf,0x84]
xxblendvd 6, 63, 21, 34
# CHECK-BE: setbc 21, 11 # encoding: [0x7e,0xab,0x03,0x00]
# CHECK-LE: setbc 21, 11 # encoding: [0x00,0x03,0xab,0x7e]
setbc 21, 11
# CHECK-BE: setbcr 21, 11 # encoding: [0x7e,0xab,0x03,0x40]
# CHECK-LE: setbcr 21, 11 # encoding: [0x40,0x03,0xab,0x7e]
setbcr 21, 11
# CHECK-BE: setnbc 21, 11 # encoding: [0x7e,0xab,0x03,0x80]
# CHECK-LE: setnbc 21, 11 # encoding: [0x80,0x03,0xab,0x7e]
setnbc 21, 11
# CHECK-BE: setnbcr 21, 11 # encoding: [0x7e,0xab,0x03,0xc0]
# CHECK-LE: setnbcr 21, 11 # encoding: [0xc0,0x03,0xab,0x7e]
setnbcr 21, 11
# CHECK-BE: vsldbi 2, 3, 4, 5 # encoding: [0x10,0x43,0x21,0x56]
# CHECK-LE: vsldbi 2, 3, 4, 5 # encoding: [0x56,0x21,0x43,0x10]
vsldbi 2, 3, 4, 5