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Simplify code a bit and make it compile better. Remove unused parameters. 

llvm-svn: 155428
This commit is contained in:
Craig Topper 2012-04-24 06:02:29 +00:00
parent ff90611253
commit 6f2a535de2
1 changed files with 10 additions and 21 deletions
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31
llvm/lib/Target/X86/X86ISelLowering.cpp
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@ -14987,18 +14987,14 @@ static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) {
return SDValue(); return SDValue();
} }
static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, static SDValue PerformUINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG) {
const X86TargetLowering *XTLI) {
SDValue Op0 = N->getOperand(0); SDValue Op0 = N->getOperand(0);
EVT InVT = Op0->getValueType(0); EVT InVT = Op0->getValueType(0);
if (!InVT.isSimple())
return SDValue();
// UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32)) // UINT_TO_FP(v4i8) -> SINT_TO_FP(ZEXT(v4i8 to v4i32))
MVT SrcVT = InVT.getSimpleVT(); if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
if (SrcVT == MVT::v8i8 || SrcVT == MVT::v4i8) {
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
MVT DstVT = (SrcVT.getVectorNumElements() == 4 ? MVT::v4i32 : MVT::v8i32); MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0); SDValue P = DAG.getNode(ISD::ZERO_EXTEND, dl, DstVT, Op0);
// Notice that we use SINT_TO_FP because we know that the high bits // Notice that we use SINT_TO_FP because we know that the high bits
// are zero and SINT_TO_FP is better supported by the hardware. // are zero and SINT_TO_FP is better supported by the hardware.
@ -15012,14 +15008,11 @@ static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
const X86TargetLowering *XTLI) { const X86TargetLowering *XTLI) {
SDValue Op0 = N->getOperand(0); SDValue Op0 = N->getOperand(0);
EVT InVT = Op0->getValueType(0); EVT InVT = Op0->getValueType(0);
if (!InVT.isSimple())
return SDValue();
// SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32)) // SINT_TO_FP(v4i8) -> SINT_TO_FP(SEXT(v4i8 to v4i32))
MVT SrcVT = InVT.getSimpleVT(); if (InVT == MVT::v8i8 || InVT == MVT::v4i8) {
if (SrcVT == MVT::v8i8 || SrcVT == MVT::v4i8) {
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
MVT DstVT = (SrcVT.getVectorNumElements() == 4 ? MVT::v4i32 : MVT::v8i32); MVT DstVT = InVT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0); SDValue P = DAG.getNode(ISD::SIGN_EXTEND, dl, DstVT, Op0);
return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P); return DAG.getNode(ISD::SINT_TO_FP, dl, N->getValueType(0), P);
} }
@ -15042,17 +15035,13 @@ static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
return SDValue(); return SDValue();
} }
static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG, static SDValue PerformFP_TO_SINTCombine(SDNode *N, SelectionDAG &DAG) {
const X86TargetLowering *XTLI) { EVT VT = N->getValueType(0);
EVT InVT = N->getValueType(0);
if (!InVT.isSimple())
return SDValue();
// v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT() // v4i8 = FP_TO_SINT() -> v4i8 = TRUNCATE (V4i32 = FP_TO_SINT()
MVT VT = InVT.getSimpleVT();
if (VT == MVT::v8i8 || VT == MVT::v4i8) { if (VT == MVT::v8i8 || VT == MVT::v4i8) {
DebugLoc dl = N->getDebugLoc(); DebugLoc dl = N->getDebugLoc();
MVT DstVT = (VT.getVectorNumElements() == 4 ? MVT::v4i32 : MVT::v8i32); MVT DstVT = VT == MVT::v4i8 ? MVT::v4i32 : MVT::v8i32;
SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0)); SDValue I = DAG.getNode(ISD::FP_TO_SINT, dl, DstVT, N->getOperand(0));
return DAG.getNode(ISD::TRUNCATE, dl, VT, I); return DAG.getNode(ISD::TRUNCATE, dl, VT, I);
} }
@ -15196,9 +15185,9 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget); case ISD::XOR: return PerformXorCombine(N, DAG, DCI, Subtarget);
case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget);
case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG, this); case ISD::UINT_TO_FP: return PerformUINT_TO_FPCombine(N, DAG);
case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG, this); case ISD::FP_TO_SINT: return PerformFP_TO_SINTCombine(N, DAG);
case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget);
case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget);
case X86ISD::FXOR: case X86ISD::FXOR: