forked from OSchip/llvm-project
[AMDGPU] Add VReg_192/VReg_224 support for MIMG instructions
Allow MIMG instructions to be selected with 6/7 VGPRs for vaddr. Previously these were rounded up to VReg_256 this saves VGPRs. Reviewed By: foad Differential Revision: https://reviews.llvm.org/D103800
This commit is contained in:
Carl Ritson
parent
45cb4140eb
commit
6efb3220b4
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@ -3448,13 +3448,11 @@ bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst) {
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if (!IsNSA) {
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if (ExpectedAddrSize > 8)
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ExpectedAddrSize = 16;
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else if (ExpectedAddrSize > 5)
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ExpectedAddrSize = 8;
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// Allow oversized 8 VGPR vaddr when only 5 VGPR are required.
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// Allow oversized 8 VGPR vaddr when only 5/6/7 VGPRs are required.
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// This provides backward compatibility for assembly created
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// before 160b types were directly supported.
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if (ExpectedAddrSize == 5 && ActualAddrSize == 8)
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// before 160b/192b/224b types were directly supported.
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if (ActualAddrSize == 8 && (ExpectedAddrSize >= 5 && ExpectedAddrSize <= 7))
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return true;
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}
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@ -730,8 +730,6 @@ DecodeStatus AMDGPUDisassembler::convertMIMGInst(MCInst &MI) const {
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if (!IsNSA) {
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if (AddrSize > 8)
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AddrSize = 16;
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else if (AddrSize > 5)
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AddrSize = 8;
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} else {
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if (AddrSize > Info->VAddrDwords) {
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// The NSA encoding does not contain enough operands for the combination
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@ -714,8 +714,10 @@ class MIMGAddrSize<int dw, bit enable_disasm> {
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!if(!eq(NumWords, 3), VReg_96,
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!if(!eq(NumWords, 4), VReg_128,
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!if(!eq(NumWords, 5), VReg_160,
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!if(!eq(NumWords, 6), VReg_192,
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!if(!eq(NumWords, 7), VReg_224,
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!if(!le(NumWords, 8), VReg_256,
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!if(!le(NumWords, 16), VReg_512, ?))))))));
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!if(!le(NumWords, 16), VReg_512, ?))))))))));
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// Whether the instruction variant with this vaddr size should be enabled for
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// the auto-generated disassembler.
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@ -733,9 +735,9 @@ class isRangeInList<int min, int max, list<int> lst> {
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bit ret = !foldl(0, lst, lhs, y, !or(lhs, !and(!le(min, y), !le(y, max))));
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}
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class MIMGAddrSizes_tmp<list<MIMGAddrSize> lst, int min> {
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list<MIMGAddrSize> List = lst;
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int Min = min;
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class MIMGAddrSizes_dw_range<list<int> range> {
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int Min = !head(range);
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int Max = !if(!empty(!tail(range)), Min, !head(!tail(range)));
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}
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class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> {
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@ -756,13 +758,17 @@ class MIMG_Sampler_AddrSizes<AMDGPUSampleVariant sample> {
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// required numbers of address words. The disassembler defaults to the
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// smallest register class.
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list<MIMGAddrSize> MachineInstrs =
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!foldl(MIMGAddrSizes_tmp<[], 0>, [1, 2, 3, 4, 5, 8, 16], lhs, dw,
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!if(isRangeInList<lhs.Min, dw, AllNumAddrWords>.ret,
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MIMGAddrSizes_tmp<
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!listconcat(lhs.List, [MIMGAddrSize<dw, !empty(lhs.List)>]),
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!if(!or(!eq(dw, 3), !eq(dw, 5)), dw, !add(dw, 1))>,
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// we still want _V4/_V8 for codegen with 3/5 dwords
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lhs)).List;
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!foldl([]<MIMGAddrSize>,
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!foreach(range,
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// V4 is generated for V3 and V4
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// V8 is generated for V5 through V8
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// V16 is generated for V9 through V16
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[[1],[2],[3],[3,4],[5],[6],[7],[5,8],[9,16]],
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MIMGAddrSizes_dw_range<range>),
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lhs, dw,
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!if(isRangeInList<dw.Min, dw.Max, AllNumAddrWords>.ret,
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!listconcat(lhs, [MIMGAddrSize<dw.Max, !empty(lhs)>]),
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lhs));
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// For NSA, generate machine instructions for all possible numbers of words
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// except 1 (which is already covered by the non-NSA case).
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@ -5846,26 +5846,10 @@ static SDValue getBuildDwordsVector(SelectionDAG &DAG, SDLoc DL,
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ArrayRef<SDValue> Elts) {
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assert(!Elts.empty());
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MVT Type;
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unsigned NumElts;
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unsigned NumElts = Elts.size();
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if (Elts.size() == 1) {
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Type = MVT::f32;
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NumElts = 1;
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} else if (Elts.size() == 2) {
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Type = MVT::v2f32;
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NumElts = 2;
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} else if (Elts.size() == 3) {
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Type = MVT::v3f32;
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NumElts = 3;
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} else if (Elts.size() <= 4) {
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Type = MVT::v4f32;
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NumElts = 4;
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} else if (Elts.size() <= 5) {
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Type = MVT::v5f32;
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NumElts = 5;
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} else if (Elts.size() <= 8) {
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Type = MVT::v8f32;
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NumElts = 8;
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if (NumElts <= 8) {
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Type = MVT::getVectorVT(MVT::f32, NumElts);
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} else {
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assert(Elts.size() <= 16);
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Type = MVT::v16f32;
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@ -4272,8 +4272,6 @@ bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
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VAddrWords = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 32;
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if (AddrWords > 8)
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AddrWords = 16;
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else if (AddrWords > 5)
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AddrWords = 8;
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}
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if (VAddrWords != AddrWords) {
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@ -1997,6 +1997,8 @@ getAnyAGPRClassForBitWidth(unsigned BitWidth) {
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return &AMDGPU::AReg_160RegClass;
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if (BitWidth <= 192)
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return &AMDGPU::AReg_192RegClass;
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if (BitWidth <= 224)
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return &AMDGPU::AReg_224RegClass;
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if (BitWidth <= 256)
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return &AMDGPU::AReg_256RegClass;
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if (BitWidth <= 512)
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@ -2019,6 +2021,8 @@ getAlignedAGPRClassForBitWidth(unsigned BitWidth) {
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return &AMDGPU::AReg_160_Align2RegClass;
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if (BitWidth <= 192)
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return &AMDGPU::AReg_192_Align2RegClass;
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if (BitWidth <= 224)
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return &AMDGPU::AReg_224_Align2RegClass;
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if (BitWidth <= 256)
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return &AMDGPU::AReg_256_Align2RegClass;
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if (BitWidth <= 512)
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@ -2055,6 +2059,8 @@ SIRegisterInfo::getSGPRClassForBitWidth(unsigned BitWidth) {
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return &AMDGPU::SGPR_160RegClass;
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if (BitWidth <= 192)
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return &AMDGPU::SGPR_192RegClass;
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if (BitWidth <= 224)
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return &AMDGPU::SGPR_224RegClass;
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if (BitWidth <= 256)
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return &AMDGPU::SGPR_256RegClass;
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if (BitWidth <= 512)
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@ -234,9 +234,12 @@ void SIShrinkInstructions::shrinkMIMG(MachineInstr &MI) {
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RC = &AMDGPU::VReg_128RegClass;
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} else if (Info->VAddrDwords == 5) {
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RC = &AMDGPU::VReg_160RegClass;
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} else if (Info->VAddrDwords <= 8) {
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} else if (Info->VAddrDwords == 6) {
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RC = &AMDGPU::VReg_192RegClass;
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} else if (Info->VAddrDwords == 7) {
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RC = &AMDGPU::VReg_224RegClass;
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} else if (Info->VAddrDwords == 8) {
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RC = &AMDGPU::VReg_256RegClass;
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NewAddrDwords = 8;
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} else {
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RC = &AMDGPU::VReg_512RegClass;
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NewAddrDwords = 16;
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@ -364,7 +364,7 @@ define amdgpu_ps <4 x float> @gather4_c_b_cl_o_2d(<8 x i32> inreg %rsrc, <4 x i3
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; GFX10-NEXT: s_mov_b32 s9, s11
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; GFX10-NEXT: s_mov_b32 s10, s12
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; GFX10-NEXT: s_mov_b32 s11, s13
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; GFX10-NEXT: image_gather4_c_b_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
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; GFX10-NEXT: image_gather4_c_b_cl_o v[0:3], v[0:5], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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@ -339,8 +339,8 @@ define amdgpu_ps void @cluster_image_sample(<8 x i32> inreg %src, <4 x i32> inre
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; GFX9-NEXT: v_mov_b32_e32 v11, v10
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; GFX9-NEXT: v_mov_b32_e32 v12, v10
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; GFX9-NEXT: v_mov_b32_e32 v13, v10
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; GFX9-NEXT: image_sample_d v[2:5], v[2:9], s[0:7], s[8:11] dmask:0xf
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; GFX9-NEXT: image_sample_d v[6:9], v[8:15], s[0:7], s[8:11] dmask:0xf
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; GFX9-NEXT: image_sample_d v[2:5], v[2:7], s[0:7], s[8:11] dmask:0xf
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; GFX9-NEXT: image_sample_d v[6:9], v[8:13], s[0:7], s[8:11] dmask:0xf
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: v_add_f32_e32 v5, v5, v9
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; GFX9-NEXT: v_add_f32_e32 v4, v4, v8
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@ -58,7 +58,7 @@ main_body:
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}
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; GCN-LABEL: {{^}}gather4_c_b_cl_o_2d:
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; GCN: image_gather4_c_b_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0x1{{$}}
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; GCN: image_gather4_c_b_cl_o v[0:3], v[0:5], s[0:7], s[8:11] dmask:0x1{{$}}
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define amdgpu_ps <4 x float> @gather4_c_b_cl_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %bias, float %zcompare, float %s, float %t, float %clamp) {
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main_body:
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%v = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.2d.v4f32.f32.f32(i32 1, i32 %offset, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
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@ -594,7 +594,7 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg
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; GFX9-NEXT: v_lshl_or_b32 v11, v7, 16, v5
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; GFX9-NEXT: v_lshl_or_b32 v9, v4, 16, v3
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; GFX9-NEXT: v_lshl_or_b32 v7, v1, 16, v0
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; GFX9-NEXT: image_sample_d v[0:3], v[7:14], s[0:7], s[8:11] dmask:0xf a16
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; GFX9-NEXT: image_sample_d v[0:3], v[7:12], s[0:7], s[8:11] dmask:0xf a16
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: ; return to shader part epilog
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;
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@ -1150,7 +1150,7 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32>
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; GFX9-NEXT: v_and_b32_e32 v0, v0, v2
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; GFX9-NEXT: v_lshl_or_b32 v11, v5, 16, v1
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; GFX9-NEXT: v_lshl_or_b32 v10, v3, 16, v0
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; GFX9-NEXT: image_sample_c_d_o v0, v[8:15], s[0:7], s[8:11] dmask:0x4 a16 da
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; GFX9-NEXT: image_sample_c_d_o v0, v[8:13], s[0:7], s[8:11] dmask:0x4 a16 da
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: ; return to shader part epilog
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;
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@ -1184,7 +1184,7 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4
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; GFX9-NEXT: v_and_b32_e32 v0, v0, v2
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; GFX9-NEXT: v_lshl_or_b32 v11, v5, 16, v1
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; GFX9-NEXT: v_lshl_or_b32 v10, v3, 16, v0
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; GFX9-NEXT: image_sample_c_d_o v[0:1], v[8:15], s[0:7], s[8:11] dmask:0x6 a16 da
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; GFX9-NEXT: image_sample_c_d_o v[0:1], v[8:13], s[0:7], s[8:11] dmask:0x6 a16 da
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: ; return to shader part epilog
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;
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@ -1160,19 +1160,19 @@ main_body:
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define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t) {
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; VERDE-LABEL: sample_d_2d:
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; VERDE: ; %bb.0: ; %main_body
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; VERDE-NEXT: image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
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; VERDE-NEXT: image_sample_d v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf
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; VERDE-NEXT: s_waitcnt vmcnt(0)
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; VERDE-NEXT: ; return to shader part epilog
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;
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; GFX6789-LABEL: sample_d_2d:
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; GFX6789: ; %bb.0: ; %main_body
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; GFX6789-NEXT: image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
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; GFX6789-NEXT: image_sample_d v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf
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; GFX6789-NEXT: s_waitcnt vmcnt(0)
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; GFX6789-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: sample_d_2d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: image_sample_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0x88,0xf0,0x00,0x00,0x40,0x00]
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; GFX10-NEXT: image_sample_d v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0x88,0xf0,0x00,0x00,0x40,0x00]
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; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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@ -1206,19 +1206,19 @@ main_body:
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define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t) {
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; VERDE-LABEL: sample_c_d_2d:
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; VERDE: ; %bb.0: ; %main_body
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; VERDE-NEXT: image_sample_c_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
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; VERDE-NEXT: image_sample_c_d v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf
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; VERDE-NEXT: s_waitcnt vmcnt(0)
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; VERDE-NEXT: ; return to shader part epilog
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;
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; GFX6789-LABEL: sample_c_d_2d:
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; GFX6789: ; %bb.0: ; %main_body
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; GFX6789-NEXT: image_sample_c_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
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; GFX6789-NEXT: image_sample_c_d v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf
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; GFX6789-NEXT: s_waitcnt vmcnt(0)
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; GFX6789-NEXT: ; return to shader part epilog
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;
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; GFX10-LABEL: sample_c_d_2d:
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; GFX10: ; %bb.0: ; %main_body
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; GFX10-NEXT: image_sample_c_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0xa8,0xf0,0x00,0x00,0x40,0x00]
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; GFX10-NEXT: image_sample_c_d v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0xa8,0xf0,0x00,0x00,0x40,0x00]
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; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
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; GFX10-NEXT: ; return to shader part epilog
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main_body:
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@ -1252,19 +1252,19 @@ main_body:
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define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %clamp) {
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; VERDE-LABEL: sample_d_cl_2d:
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; VERDE: ; %bb.0: ; %main_body
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; VERDE-NEXT: image_sample_d_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
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; VERDE-NEXT: image_sample_d_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf
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; VERDE-NEXT: s_waitcnt vmcnt(0)
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; VERDE-NEXT: ; return to shader part epilog
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;
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; GFX6789-LABEL: sample_d_cl_2d:
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; GFX6789: ; %bb.0: ; %main_body
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; GFX6789-NEXT: image_sample_d_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
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; GFX6789-NEXT: image_sample_d_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf
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; GFX6789-NEXT: s_waitcnt vmcnt(0)
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; GFX6789-NEXT: ; return to shader part epilog
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;
|
||||
; GFX10-LABEL: sample_d_cl_2d:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: image_sample_d_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0x8c,0xf0,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: image_sample_d_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0x8c,0xf0,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
|
|
@ -1344,19 +1344,19 @@ main_body:
|
|||
define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t) {
|
||||
; VERDE-LABEL: sample_cd_2d:
|
||||
; VERDE: ; %bb.0: ; %main_body
|
||||
; VERDE-NEXT: image_sample_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
|
||||
; VERDE-NEXT: image_sample_cd v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf
|
||||
; VERDE-NEXT: s_waitcnt vmcnt(0)
|
||||
; VERDE-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX6789-LABEL: sample_cd_2d:
|
||||
; GFX6789: ; %bb.0: ; %main_body
|
||||
; GFX6789-NEXT: image_sample_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
|
||||
; GFX6789-NEXT: image_sample_cd v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf
|
||||
; GFX6789-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX6789-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-LABEL: sample_cd_2d:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: image_sample_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0xa0,0xf1,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: image_sample_cd v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0xa0,0xf1,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
|
|
@ -1390,19 +1390,19 @@ main_body:
|
|||
define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t) {
|
||||
; VERDE-LABEL: sample_c_cd_2d:
|
||||
; VERDE: ; %bb.0: ; %main_body
|
||||
; VERDE-NEXT: image_sample_c_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
|
||||
; VERDE-NEXT: image_sample_c_cd v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf
|
||||
; VERDE-NEXT: s_waitcnt vmcnt(0)
|
||||
; VERDE-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX6789-LABEL: sample_c_cd_2d:
|
||||
; GFX6789: ; %bb.0: ; %main_body
|
||||
; GFX6789-NEXT: image_sample_c_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
|
||||
; GFX6789-NEXT: image_sample_c_cd v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf
|
||||
; GFX6789-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX6789-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-LABEL: sample_c_cd_2d:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: image_sample_c_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0xa8,0xf1,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: image_sample_c_cd v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0xa8,0xf1,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
|
|
@ -1436,19 +1436,19 @@ main_body:
|
|||
define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, float %clamp) {
|
||||
; VERDE-LABEL: sample_cd_cl_2d:
|
||||
; VERDE: ; %bb.0: ; %main_body
|
||||
; VERDE-NEXT: image_sample_cd_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
|
||||
; VERDE-NEXT: image_sample_cd_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf
|
||||
; VERDE-NEXT: s_waitcnt vmcnt(0)
|
||||
; VERDE-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX6789-LABEL: sample_cd_cl_2d:
|
||||
; GFX6789: ; %bb.0: ; %main_body
|
||||
; GFX6789-NEXT: image_sample_cd_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf
|
||||
; GFX6789-NEXT: image_sample_cd_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf
|
||||
; GFX6789-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX6789-NEXT: ; return to shader part epilog
|
||||
;
|
||||
; GFX10-LABEL: sample_cd_cl_2d:
|
||||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: image_sample_cd_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0xa4,0xf1,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: image_sample_cd_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0xa4,0xf1,0x00,0x00,0x40,0x00]
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0) ; encoding: [0x70,0x3f,0x8c,0xbf]
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
|
|
|
|||
|
|
@ -92,7 +92,7 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
|
|||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
||||
; GFX10-NEXT: v_lshl_or_b32 v5, v6, 16, v5
|
||||
; GFX10-NEXT: image_sample_c_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10-NEXT: image_sample_c_d v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
;
|
||||
|
|
@ -100,7 +100,7 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr
|
|||
; GFX10GISEL: ; %bb.0: ; %main_body
|
||||
; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v5, 0xffff, v5, v6
|
||||
; GFX10GISEL-NEXT: image_sample_c_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: image_sample_c_d v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10GISEL-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
|
|
@ -145,7 +145,7 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in
|
|||
; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v4, v4, v7, v5
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v5, v6, v7, s12
|
||||
; GFX10GISEL-NEXT: image_sample_d_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: image_sample_d_cl v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10GISEL-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
|
|
@ -190,7 +190,7 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
|
|||
; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v5, v5, v8, v6
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v6, v7, v8, s12
|
||||
; GFX10GISEL-NEXT: image_sample_c_d_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: image_sample_c_d_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10GISEL-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
|
|
@ -262,7 +262,7 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in
|
|||
; GFX10: ; %bb.0: ; %main_body
|
||||
; GFX10-NEXT: v_and_b32_e32 v5, 0xffff, v5
|
||||
; GFX10-NEXT: v_lshl_or_b32 v5, v6, 16, v5
|
||||
; GFX10-NEXT: image_sample_c_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10-NEXT: image_sample_c_cd v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10-NEXT: ; return to shader part epilog
|
||||
;
|
||||
|
|
@ -270,7 +270,7 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in
|
|||
; GFX10GISEL: ; %bb.0: ; %main_body
|
||||
; GFX10GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v5, 0xffff, v5, v6
|
||||
; GFX10GISEL-NEXT: image_sample_c_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: image_sample_c_cd v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10GISEL-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
|
|
@ -315,7 +315,7 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i
|
|||
; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v4, v4, v7, v5
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v5, v6, v7, s12
|
||||
; GFX10GISEL-NEXT: image_sample_cd_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: image_sample_cd_cl v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10GISEL-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
|
|
@ -360,7 +360,7 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32>
|
|||
; GFX10GISEL-NEXT: s_lshl_b32 s12, s0, 16
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v5, v5, v8, v6
|
||||
; GFX10GISEL-NEXT: v_and_or_b32 v6, v7, v8, s12
|
||||
; GFX10GISEL-NEXT: image_sample_c_cd_cl v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: image_sample_c_cd_cl v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10GISEL-NEXT: s_waitcnt vmcnt(0)
|
||||
; GFX10GISEL-NEXT: ; return to shader part epilog
|
||||
main_body:
|
||||
|
|
|
|||
|
|
@ -122,7 +122,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_b_cl_o_2d:
|
||||
; GCN: image_sample_c_b_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_c_b_cl_o v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_b_cl_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %bias, float %zcompare, float %s, float %t, float %clamp) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.2d.v4f32.f32.f32(i32 15, i32 %offset, float %bias, float %zcompare, float %s, float %t, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
@ -138,7 +138,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_d_o_2d:
|
||||
; GCN: image_sample_d_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_d_o v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_d_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.d.o.2d.v4f32.f32.f32(i32 15, i32 %offset, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
@ -178,7 +178,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_d_cl_o_1d:
|
||||
; GCN: image_sample_c_d_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_c_d_cl_o v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_d_cl_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
@ -202,7 +202,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_cd_o_2d:
|
||||
; GCN: image_sample_cd_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_cd_o v[0:3], v[0:6], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_cd_o_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.cd.o.2d.v4f32.f32.f32(i32 15, i32 %offset, float %dsdh, float %dtdh, float %dsdv, float %dtdv, float %s, float %t, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
@ -242,7 +242,7 @@ main_body:
|
|||
}
|
||||
|
||||
; GCN-LABEL: {{^}}sample_c_cd_cl_o_1d:
|
||||
; GCN: image_sample_c_cd_cl_o v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
; GCN: image_sample_c_cd_cl_o v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf{{$}}
|
||||
define amdgpu_ps <4 x float> @sample_c_cd_cl_o_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp) {
|
||||
main_body:
|
||||
%v = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.1d.v4f32.f32.f32(i32 15, i32 %offset, float %zcompare, float %dsdh, float %dsdv, float %s, float %clamp, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)
|
||||
|
|
|
|||
|
|
@ -172,8 +172,8 @@ image_sample_d v[64:66], [v32, v16, v8], s[4:11], s[100:103] dmask:0x7 dim:SQ_RS
|
|||
image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D
|
||||
; GFX10: image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D ; encoding: [0x0c,0x07,0x88,0xf0,0x20,0x40,0x21,0x03,0x10,0x08,0x04,0x02,0x01,0x00,0x00,0x00]
|
||||
|
||||
image_sample_d v[64:66], v[32:39], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D
|
||||
; GFX10: image_sample_d v[64:66], v[32:39], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x07,0x88,0xf0,0x20,0x40,0x21,0x03]
|
||||
image_sample_d v[64:66], v[32:37], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D
|
||||
; GFX10: image_sample_d v[64:66], v[32:37], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x07,0x88,0xf0,0x20,0x40,0x21,0x03]
|
||||
|
||||
image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1, v0, v20, v21], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D
|
||||
; GFX10: image_sample_d v[64:66], [v32, v16, v8, v4, v2, v1, v0, v20, v21], s[4:11], s[100:103] dmask:0x7 dim:SQ_RSRC_IMG_3D ; encoding: [0x14,0x07,0x88,0xf0,0x20,0x40,0x21,0x03,0x10,0x08,0x04,0x02,0x01,0x00,0x14,0x15]
|
||||
|
|
@ -424,8 +424,8 @@ image_sample_d v[0:3], [v0, v1, v2, v3, v4, v5, v6, v8], s[0:7], s[8:11] dmask:0
|
|||
image_sample_c_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
|
||||
; GFX10: image_sample_c_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x00,0x0f,0xa8,0xf0,0x00,0x00,0x40,0x40]
|
||||
|
||||
image_sample_c_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10: image_sample_c_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0xa8,0xf0,0x00,0x00,0x40,0x40]
|
||||
image_sample_c_d v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10: image_sample_c_d v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0xa8,0xf0,0x00,0x00,0x40,0x40]
|
||||
|
||||
image_sample_d_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
|
||||
; GFX10: image_sample_d_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x00,0x0f,0x8c,0xf0,0x00,0x00,0x40,0x40]
|
||||
|
|
@ -448,8 +448,8 @@ image_sample_cd v[0:3], v[0:4], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
|||
image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
|
||||
; GFX10: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x00,0x0f,0xa8,0xf1,0x00,0x00,0x40,0x40]
|
||||
|
||||
image_sample_c_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10: image_sample_c_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0xa8,0xf1,0x00,0x00,0x40,0x40]
|
||||
image_sample_c_cd v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16
|
||||
; GFX10: image_sample_c_cd v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0xa8,0xf1,0x00,0x00,0x40,0x40]
|
||||
|
||||
image_sample_cd_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16
|
||||
; GFX10: image_sample_cd_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x00,0x0f,0xa4,0xf1,0x00,0x00,0x40,0x40]
|
||||
|
|
|
|||
|
|
@ -255,10 +255,7 @@
|
|||
# GFX10: image_sample_c_b v[16:19], v[8:12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x18,0x0f,0xb4,0xf0,0x08,0x10,0x25,0x03]
|
||||
0x18,0x0f,0xb4,0xf0,0x08,0x10,0x25,0x03
|
||||
|
||||
# TODO: address of this instruction is v[250:255], but this register class does
|
||||
# not exist, and the next-larger size goes beyond the last register, so
|
||||
# the disassembly is not adjusted properly
|
||||
# GFX10: image_sample_c_b_cl v16, v[250:252], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x18,0x0f,0xb8,0xf0,0xfa,0x10,0x25,0x03]
|
||||
# GFX10: image_sample_c_b_cl v[16:19], v[250:255], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x18,0x0f,0xb8,0xf0,0xfa,0x10,0x25,0x03]
|
||||
0x18,0x0f,0xb8,0xf0,0xfa,0x10,0x25,0x03
|
||||
|
||||
# GFX10: image_sample_c_lz v[16:19], v[253:255], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0xbc,0xf0,0xfd,0x10,0x25,0x03]
|
||||
|
|
|
|||
|
|
@ -120,7 +120,7 @@
|
|||
# GFX10: image_sample_c_d v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x00,0x0f,0xa8,0xf0,0x00,0x00,0x40,0x40]
|
||||
0x00,0x0f,0xa8,0xf0,0x00,0x00,0x40,0x40
|
||||
|
||||
# GFX10: image_sample_c_d v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0xa8,0xf0,0x00,0x00,0x40,0x40]
|
||||
# GFX10: image_sample_c_d v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0xa8,0xf0,0x00,0x00,0x40,0x40]
|
||||
0x08,0x0f,0xa8,0xf0,0x00,0x00,0x40,0x40
|
||||
|
||||
# GFX10: image_sample_d_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x00,0x0f,0x8c,0xf0,0x00,0x00,0x40,0x40]
|
||||
|
|
@ -144,7 +144,7 @@
|
|||
# GFX10: image_sample_c_cd v[0:3], v[0:3], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x00,0x0f,0xa8,0xf1,0x00,0x00,0x40,0x40]
|
||||
0x00,0x0f,0xa8,0xf1,0x00,0x00,0x40,0x40
|
||||
|
||||
# GFX10: image_sample_c_cd v[0:3], v[0:7], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0xa8,0xf1,0x00,0x00,0x40,0x40]
|
||||
# GFX10: image_sample_c_cd v[0:3], v[0:5], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; encoding: [0x08,0x0f,0xa8,0xf1,0x00,0x00,0x40,0x40]
|
||||
0x08,0x0f,0xa8,0xf1,0x00,0x00,0x40,0x40
|
||||
|
||||
# GFX10: image_sample_cd_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; encoding: [0x00,0x0f,0xa4,0xf1,0x00,0x00,0x40,0x40]
|
||||
|
|
|
|||
Loading…
Reference in New Issue