forked from OSchip/llvm-project
[RISCV] Precommit test for D122634
This is a recommit of360d44e, which was reverted inb1620d4because it caused some errors due to no `nounwind` attrs in `machine-outliner-cfi.mir`. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D123364
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wangpc
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6ee890b79e
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# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=OUTLINED,RV32I-MO %s
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# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=OUTLINED,RV64I-MO %s
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# CFIs are invisible (they can be outlined, but won't actually impact the outlining result) if there
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# is no need to unwind. CFIs will be stripped when we build outlined functions.
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--- |
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define void @func1(i32 %a, i32 %b) nounwind { ret void }
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define void @func2(i32 %a, i32 %b) nounwind { ret void }
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define void @func3(i32 %a, i32 %b) nounwind { ret void }
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...
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---
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name: func1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: func1
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV32I-MO-NEXT: PseudoRET
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; RV64I-MO-LABEL: name: func1
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV64I-MO-NEXT: PseudoRET
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$x10 = ORI $x10, 1023
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CFI_INSTRUCTION offset $x1, 0
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$x11 = ORI $x11, 1023
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CFI_INSTRUCTION offset $x1, -4
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$x12 = ADDI $x10, 17
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CFI_INSTRUCTION offset $x1, -8
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$x11 = AND $x12, $x11
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CFI_INSTRUCTION offset $x1, -12
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$x10 = SUB $x10, $x11
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PseudoRET
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...
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---
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name: func2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: func2
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV32I-MO-NEXT: PseudoRET
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; RV64I-MO-LABEL: name: func2
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV64I-MO-NEXT: PseudoRET
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$x10 = ORI $x10, 1023
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CFI_INSTRUCTION offset $x1, 0
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$x11 = ORI $x11, 1023
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CFI_INSTRUCTION offset $x1, -8
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$x12 = ADDI $x10, 17
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CFI_INSTRUCTION offset $x1, -4
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$x11 = AND $x12, $x11
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CFI_INSTRUCTION offset $x1, -12
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$x10 = SUB $x10, $x11
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PseudoRET
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...
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---
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name: func3
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: func3
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV32I-MO-NEXT: PseudoRET
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; RV64I-MO-LABEL: name: func3
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV64I-MO-NEXT: PseudoRET
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$x10 = ORI $x10, 1023
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CFI_INSTRUCTION offset $x1, -12
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$x11 = ORI $x11, 1023
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CFI_INSTRUCTION offset $x1, -8
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$x12 = ADDI $x10, 17
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CFI_INSTRUCTION offset $x1, -4
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$x11 = AND $x12, $x11
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CFI_INSTRUCTION offset $x1, 0
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$x10 = SUB $x10, $x11
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PseudoRET
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# OUTLINED-LABEL: name: OUTLINED_FUNCTION_0
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# OUTLINED: liveins: $x11, $x10, $x5
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# OUTLINED-NEXT: {{ $}}
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# OUTLINED-NEXT: $x10 = ORI $x10, 1023
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# OUTLINED-NEXT: $x11 = ORI $x11, 1023
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# OUTLINED-NEXT: $x12 = ADDI $x10, 17
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# OUTLINED-NEXT: $x11 = AND $x12, $x11
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# OUTLINED-NEXT: $x10 = SUB $x10, $x11
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# OUTLINED-NEXT: $x0 = JALR $x5, 0
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@ -0,0 +1,99 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=RV32I-MO %s
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# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
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# RUN: | FileCheck -check-prefixes=RV64I-MO %s
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# Position instructions are illegal to outline. The first instruction won't be outlined
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# because position instructions break the sequence.
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--- |
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define void @func1(i32 %a, i32 %b) { ret void }
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define void @func2(i32 %a, i32 %b) { ret void }
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define void @func3(i32 %a, i32 %b) { ret void }
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...
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---
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name: func1
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: func1
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV32I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0>
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; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV32I-MO-NEXT: PseudoRET
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; RV64I-MO-LABEL: name: func1
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV64I-MO-NEXT: EH_LABEL <mcsymbol .Ltmp0>
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; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV64I-MO-NEXT: PseudoRET
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$x10 = ORI $x10, 1023
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EH_LABEL <mcsymbol .Ltmp0>
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET
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...
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---
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name: func2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: func2
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV32I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1>
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; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV32I-MO-NEXT: PseudoRET
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; RV64I-MO-LABEL: name: func2
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV64I-MO-NEXT: GC_LABEL <mcsymbol .Ltmp1>
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; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV64I-MO-NEXT: PseudoRET
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$x10 = ORI $x10, 1023
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GC_LABEL <mcsymbol .Ltmp1>
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET
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...
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---
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name: func3
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x10, $x11
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; RV32I-MO-LABEL: name: func3
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; RV32I-MO: liveins: $x10, $x11
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; RV32I-MO-NEXT: {{ $}}
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; RV32I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV32I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2>
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; RV32I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV32I-MO-NEXT: PseudoRET
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; RV64I-MO-LABEL: name: func3
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; RV64I-MO: liveins: $x10, $x11
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; RV64I-MO-NEXT: {{ $}}
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; RV64I-MO-NEXT: $x10 = ORI $x10, 1023
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; RV64I-MO-NEXT: ANNOTATION_LABEL <mcsymbol .Ltmp2>
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; RV64I-MO-NEXT: $x5 = PseudoCALLReg target-flags(riscv-call) @OUTLINED_FUNCTION_0, implicit-def $x5, implicit-def $x10, implicit-def $x11, implicit-def $x12, implicit $x10, implicit $x11
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; RV64I-MO-NEXT: PseudoRET
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$x10 = ORI $x10, 1023
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ANNOTATION_LABEL <mcsymbol .Ltmp2>
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$x11 = ORI $x11, 1023
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$x12 = ADDI $x10, 17
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$x11 = AND $x12, $x11
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$x10 = SUB $x10, $x11
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PseudoRET
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@ -0,0 +1,58 @@
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; RUN: llc -verify-machineinstrs -enable-machine-outliner -mattr=+m -mtriple=riscv64 < %s | FileCheck %s
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; Ensure that we won't outline CFIs when they are needed in unwinding.
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define i32 @func1(i32 %x) #0 {
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; CHECK-LABEL: func1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: call t0, OUTLINED_FUNCTION_0
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; CHECK-NEXT: call __cxa_allocate_exception@plt
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; CHECK-NEXT: sw s0, 0(a0)
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; CHECK-NEXT: lui a1, %hi(_ZTIi)
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; CHECK-NEXT: addi a1, a1, %lo(_ZTIi)
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; CHECK-NEXT: li a2, 0
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; CHECK-NEXT: call __cxa_throw@plt
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entry:
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%mul = mul i32 %x, %x
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%add = add i32 %mul, 1
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%exception = tail call i8* @__cxa_allocate_exception(i64 4)
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%0 = bitcast i8* %exception to i32*
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store i32 %add, i32* %0
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tail call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null)
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unreachable
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}
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define i32 @func2(i32 %x) #0 {
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; CHECK-LABEL: func2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: call t0, OUTLINED_FUNCTION_0
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; CHECK-NEXT: call __cxa_allocate_exception@plt
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; CHECK-NEXT: sw s0, 0(a0)
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; CHECK-NEXT: lui a1, %hi(_ZTIi)
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; CHECK-NEXT: addi a1, a1, %lo(_ZTIi)
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; CHECK-NEXT: li a2, 0
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; CHECK-NEXT: call __cxa_throw@plt
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entry:
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%mul = mul i32 %x, %x
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%add = add i32 %mul, 1
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%exception = tail call i8* @__cxa_allocate_exception(i64 4)
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%0 = bitcast i8* %exception to i32*
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store i32 %add, i32* %0
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tail call void @__cxa_throw(i8* %exception, i8* bitcast (i8** @_ZTIi to i8*), i8* null)
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unreachable
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}
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; CHECK-LABEL: OUTLINED_FUNCTION_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addi sp, sp, -16
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; CHECK-NEXT: sd ra, 8(sp)
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; CHECK-NEXT: sd s0, 0(sp)
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; CHECK-NEXT: mulw a0, a0, a0
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; CHECK-NEXT: addiw s0, a0, 1
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; CHECK-NEXT: li a0, 4
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@_ZTIi = external constant i8*
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declare i8* @__cxa_allocate_exception(i64)
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declare void @__cxa_throw(i8*, i8*, i8*)
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attributes #0 = { minsize noreturn }
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