forked from OSchip/llvm-project
[AVR] Add the machine code emitter
Reviewers: arsenm, kparzysz Subscribers: wdng, beanz, japaric, llvm-commits, mgorny Differential Revision: https://reviews.llvm.org/D25388 llvm-svn: 285269
This commit is contained in:
Dylan McKay
parent
09dd423a7d
commit
6eaa4e4bcc
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//===-- AVRMCCodeEmitter.cpp - Convert AVR Code to Machine Code -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AVRMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "AVRMCCodeEmitter.h"
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#include "MCTargetDesc/AVRMCExpr.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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#include "llvm/ADT/APFloat.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCFixup.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/raw_ostream.h"
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#define DEBUG_TYPE "mccodeemitter"
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#define GET_INSTRMAP_INFO
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#include "AVRGenInstrInfo.inc"
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#undef GET_INSTRMAP_INFO
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namespace llvm {
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/// Performs a post-encoding step on a `LD` or `ST` instruction.
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///
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/// The encoding of the LD/ST family of instructions is inconsistent w.r.t
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/// the pointer register and the addressing mode.
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///
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/// The permutations of the format are as followed:
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/// ld Rd, X `1001 000d dddd 1100`
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/// ld Rd, X+ `1001 000d dddd 1101`
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/// ld Rd, -X `1001 000d dddd 1110`
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///
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/// ld Rd, Y `1000 000d dddd 1000`
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/// ld Rd, Y+ `1001 000d dddd 1001`
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/// ld Rd, -Y `1001 000d dddd 1010`
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///
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/// ld Rd, Z `1000 000d dddd 0000`
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/// ld Rd, Z+ `1001 000d dddd 0001`
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/// ld Rd, -Z `1001 000d dddd 0010`
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/// ^
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/// |
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/// Note this one inconsistent bit - it is 1 sometimes and 0 at other times.
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/// There is no logical pattern. Looking at a truth table, the following
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/// formula can be derived to fit the pattern:
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//
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/// ```
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/// inconsistent_bit = is_predec OR is_postinc OR is_reg_x
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/// ```
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//
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/// We manually set this bit in this post encoder method.
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unsigned
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AVRMCCodeEmitter::loadStorePostEncoder(const MCInst &MI, unsigned EncodedValue,
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const MCSubtargetInfo &STI) const {
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assert(MI.getOperand(0).isReg() && MI.getOperand(1).isReg() &&
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"the load/store operands must be registers");
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unsigned Opcode = MI.getOpcode();
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// check whether either of the registers are the X pointer register.
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bool IsRegX = MI.getOperand(0).getReg() == AVR::R27R26 ||
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MI.getOperand(1).getReg() == AVR::R27R26;
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bool IsPredec = Opcode == AVR::LDRdPtrPd || Opcode == AVR::STPtrPdRr;
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bool IsPostinc = Opcode == AVR::LDRdPtrPi || Opcode == AVR::STPtrPiRr;
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// Check if we need to set the inconsistent bit
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if (IsRegX || IsPredec || IsPostinc) {
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EncodedValue |= (1 << 12);
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}
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return EncodedValue;
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}
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template <AVR::Fixups Fixup>
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unsigned
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AVRMCCodeEmitter::encodeRelCondBrTarget(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isExpr()) {
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Fixups.push_back(MCFixup::create(0, MO.getExpr(),
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MCFixupKind(Fixup), MI.getLoc()));
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return 0;
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}
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assert(MO.isImm());
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// Take the size of the current instruction away.
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// With labels, this is implicitly done.
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auto target = MO.getImm();
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AVR::fixups::adjustBranchTarget(target);
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return target;
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}
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unsigned AVRMCCodeEmitter::encodeLDSTPtrReg(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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auto MO = MI.getOperand(OpNo);
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// The operand should be a pointer register.
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assert(MO.isReg());
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switch (MO.getReg()) {
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case AVR::R27R26: return 0x03; // X: 0b11
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case AVR::R29R28: return 0x02; // Y: 0b10
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case AVR::R31R30: return 0x00; // Z: 0b00
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default:
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llvm_unreachable("invalid pointer register");
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}
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}
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/// Encodes a `memri` operand.
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/// The operand is 7-bits.
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/// * The lower 6 bits is the immediate
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/// * The upper bit is the pointer register bit (Z=0,Y=1)
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unsigned AVRMCCodeEmitter::encodeMemri(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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auto RegOp = MI.getOperand(OpNo);
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auto OffsetOp = MI.getOperand(OpNo + 1);
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assert(RegOp.isReg() && "Expected register operand");
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uint8_t RegBit = 0;
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switch (RegOp.getReg()) {
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default:
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llvm_unreachable("Expected either Y or Z register");
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case AVR::R31R30:
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RegBit = 0;
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break; // Z register
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case AVR::R29R28:
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RegBit = 1;
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break; // Y register
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}
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int8_t OffsetBits;
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if (OffsetOp.isImm()) {
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OffsetBits = OffsetOp.getImm();
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} else if (OffsetOp.isExpr()) {
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OffsetBits = 0;
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Fixups.push_back(MCFixup::create(0, OffsetOp.getExpr(),
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MCFixupKind(AVR::fixup_6), MI.getLoc()));
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} else {
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llvm_unreachable("invalid value for offset");
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}
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return (RegBit << 6) | OffsetBits;
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}
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unsigned AVRMCCodeEmitter::encodeComplement(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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// The operand should be an immediate.
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assert(MI.getOperand(OpNo).isImm());
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auto Imm = MI.getOperand(OpNo).getImm();
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return (~0) - Imm;
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}
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template <AVR::Fixups Fixup>
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unsigned AVRMCCodeEmitter::encodeImm(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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auto MO = MI.getOperand(OpNo);
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if (MO.isExpr()) {
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if (isa<AVRMCExpr>(MO.getExpr())) {
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// If the expression is already an AVRMCExpr (i.e. a lo8(symbol),
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// we shouldn't perform any more fixups. Without this check, we would
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// instead create a fixup to the symbol named 'lo8(symbol)' which
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// is not correct.
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return getExprOpValue(MO.getExpr(), Fixups, STI);
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}
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MCFixupKind FixupKind = static_cast<MCFixupKind>(Fixup);
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Fixups.push_back(MCFixup::create(0, MO.getExpr(), FixupKind, MI.getLoc()));
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return 0;
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}
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assert(MO.isImm());
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return MO.getImm();
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}
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unsigned AVRMCCodeEmitter::encodeCallTarget(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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auto MO = MI.getOperand(OpNo);
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if (MO.isExpr()) {
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MCFixupKind FixupKind = static_cast<MCFixupKind>(AVR::fixup_call);
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Fixups.push_back(MCFixup::create(0, MO.getExpr(), FixupKind, MI.getLoc()));
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return 0;
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}
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assert(MO.isImm());
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auto Target = MO.getImm();
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AVR::fixups::adjustBranchTarget(Target);
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return Target;
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}
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unsigned AVRMCCodeEmitter::getExprOpValue(const MCExpr *Expr,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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MCExpr::ExprKind Kind = Expr->getKind();
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if (Kind == MCExpr::Binary) {
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Expr = static_cast<const MCBinaryExpr *>(Expr)->getLHS();
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Kind = Expr->getKind();
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}
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if (Kind == MCExpr::Target) {
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AVRMCExpr const *AVRExpr = cast<AVRMCExpr>(Expr);
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int64_t Result;
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if (AVRExpr->evaluateAsConstant(Result)) {
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return Result;
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}
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MCFixupKind FixupKind = static_cast<MCFixupKind>(AVRExpr->getFixupKind());
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Fixups.push_back(MCFixup::create(0, AVRExpr, FixupKind));
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return 0;
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}
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assert(Kind == MCExpr::SymbolRef);
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return 0;
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}
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unsigned AVRMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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if (MO.isReg()) return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
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if (MO.isImm()) return static_cast<unsigned>(MO.getImm());
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if (MO.isFPImm())
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return static_cast<unsigned>(APFloat(MO.getFPImm())
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.bitcastToAPInt()
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.getHiBits(32)
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.getLimitedValue());
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// MO must be an Expr.
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assert(MO.isExpr());
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return getExprOpValue(MO.getExpr(), Fixups, STI);
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}
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void AVRMCCodeEmitter::emitInstruction(uint64_t Val, unsigned Size,
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const MCSubtargetInfo &STI,
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raw_ostream &OS) const {
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const uint16_t *Words = reinterpret_cast<uint16_t const *>(&Val);
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size_t WordCount = Size / 2;
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for (int64_t i = WordCount - 1; i >= 0; --i) {
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uint16_t Word = Words[i];
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OS << (uint8_t) ((Word & 0x00ff) >> 0);
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OS << (uint8_t) ((Word & 0xff00) >> 8);
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}
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}
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void AVRMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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// Get byte count of instruction
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unsigned Size = Desc.getSize();
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assert(Size > 0 && "Instruction size cannot be zero");
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uint64_t BinaryOpCode = getBinaryCodeForInstr(MI, Fixups, STI);
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emitInstruction(BinaryOpCode, Size, STI, OS);
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}
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MCCodeEmitter *createAVRMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx) {
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return new AVRMCCodeEmitter(MCII, Ctx);
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}
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#include "AVRGenMCCodeEmitter.inc"
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} // end of namespace llvm
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@ -0,0 +1,115 @@
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//===-- AVRMCCodeEmitter.h - Convert AVR Code to Machine Code -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the AVRMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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//
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#ifndef LLVM_AVR_CODE_EMITTER_H
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#define LLVM_AVR_CODE_EMITTER_H
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#include "AVRFixupKinds.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/Support/DataTypes.h"
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#define GET_INSTRINFO_OPERAND_TYPES_ENUM
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#include "AVRGenInstrInfo.inc"
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namespace llvm {
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class MCContext;
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class MCExpr;
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class MCFixup;
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class MCInst;
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class MCInstrInfo;
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class MCOperand;
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class MCSubtargetInfo;
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class raw_ostream;
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/// Writes AVR machine code to a stream.
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class AVRMCCodeEmitter : public MCCodeEmitter {
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public:
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AVRMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
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: MCII(MCII), Ctx(Ctx) {}
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private:
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/// Finishes up encoding an LD/ST instruction.
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/// The purpose of this function is to set an bit in the instruction
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/// which follows no logical pattern. See the implementation for details.
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unsigned loadStorePostEncoder(const MCInst &MI, unsigned EncodedValue,
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const MCSubtargetInfo &STI) const;
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/// Gets the encoding for a conditional branch target.
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template <AVR::Fixups Fixup>
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unsigned encodeRelCondBrTarget(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Encodes the `PTRREGS` operand to a load or store instruction.
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unsigned encodeLDSTPtrReg(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Encodes a `register+immediate` operand for `LDD`/`STD`.
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unsigned encodeMemri(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Takes the compliment of a number (~0 - val).
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unsigned encodeComplement(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Encodes an immediate value with a given fixup.
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template <AVR::Fixups Fixup>
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unsigned encodeImm(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Gets the encoding of the target for the `CALL k` instruction.
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unsigned encodeCallTarget(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// TableGen'ed function to get the binary encoding for an instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Returns the binary encoding of operand.
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///
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/// If the machine operand requires relocation, the relocation is recorded
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/// and zero is returned.
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unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
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raw_ostream &OS) const;
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void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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AVRMCCodeEmitter(const AVRMCCodeEmitter &) = delete;
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void operator=(const AVRMCCodeEmitter &) = delete;
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const MCInstrInfo &MCII;
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MCContext &Ctx;
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};
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} // end namespace of llvm.
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#endif // LLVM_AVR_CODE_EMITTER_H
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@ -101,6 +101,9 @@ extern "C" void LLVMInitializeAVRTargetMC() {
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TargetRegistry::RegisterMCInstPrinter(getTheAVRTarget(),
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createAVRMCInstPrinter);
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// Register the MC Code Emitter
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TargetRegistry::RegisterMCCodeEmitter(TheAVRTarget, createAVRMCCodeEmitter);
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// Register the ELF streamer
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TargetRegistry::RegisterELFStreamer(getTheAVRTarget(), createMCStreamer);
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@ -3,6 +3,7 @@ add_llvm_library(LLVMAVRDesc
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AVRELFObjectWriter.cpp
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AVRELFStreamer.cpp
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AVRMCAsmInfo.cpp
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AVRMCCodeEmitter.cpp
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AVRMCExpr.cpp
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AVRMCTargetDesc.cpp
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AVRTargetStreamer.cpp
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