From 6e9b9978cfb71b3c5de315dbc628e5909baa71da Mon Sep 17 00:00:00 2001
From: Roman Lebedev <lebedev.ri@gmail.com>
Date: Sat, 13 Mar 2021 15:11:12 +0300
Subject: [PATCH] [LSR] Don't try to fixup uses in 'EH pad' instructions

The added test case crashes before this fix:
```
opt: /repositories/llvm-project/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp:5172: BasicBlock::iterator (anonymous namespace)::LSRInstance::AdjustInsertPositionForExpand(BasicBlock::iterator, const (anonymous namespace)::LSRFixup &, const (anonymous namespace)::LSRUse &, llvm::SCEVExpander &) const: Assertion `!isa<PHINode>(LowestIP) && !LowestIP->isEHPad() && !isa<DbgInfoIntrinsic>(LowestIP) && "Insertion point must be a normal instruction"' failed.
```
This is fully analogous to the previous commit,
with the pointer constant replaced to be something non-null.

The comparison here can be strength-reduced,
but the second operand of the comparison happens to be identical
to the constant pointer in the `catch` case of `landingpad`.

While LSRInstance::CollectLoopInvariantFixupsAndFormulae()
already gave up on uses in blocks ending up with EH pads,
it didn't consider this case.

Eventually, `LSRInstance::AdjustInsertPositionForExpand()`
will be called, but the original insertion point it will get
is the user instruction itself, and it doesn't want to
deal with EH pads, and asserts as much.

It would seem that this basically never happens in-the-wild,
otherwise it would have been reported already,
so it seems safe to take the cautious approach,
and just not deal with such users.
---
 .../Transforms/Scalar/LoopStrengthReduce.cpp  |  3 ++
 .../X86/eh-insertion-point-2.ll               | 47 +++++++++++++++++++
 2 files changed, 50 insertions(+)
 create mode 100644 llvm/test/Transforms/LoopStrengthReduce/X86/eh-insertion-point-2.ll

diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index d67266330396..ae1ed681d998 100644
--- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -3430,6 +3430,9 @@ LSRInstance::CollectLoopInvariantFixupsAndFormulae() {
         // Ignore non-instructions.
         if (!UserInst)
           continue;
+        // Don't bother if the instruction is an EHPad.
+        if (UserInst->isEHPad())
+          continue;
         // Ignore instructions in other functions (as can happen with
         // Constants).
         if (UserInst->getParent()->getParent() != L->getHeader()->getParent())
diff --git a/llvm/test/Transforms/LoopStrengthReduce/X86/eh-insertion-point-2.ll b/llvm/test/Transforms/LoopStrengthReduce/X86/eh-insertion-point-2.ll
new file mode 100644
index 000000000000..6aced7c58e22
--- /dev/null
+++ b/llvm/test/Transforms/LoopStrengthReduce/X86/eh-insertion-point-2.ll
@@ -0,0 +1,47 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -S -loop-reduce < %s | FileCheck %s
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+declare void @maybe_throws()
+declare void @use1(i1)
+
+define void @is_not_42(i8* %baseptr, i8* %finalptr) local_unnamed_addr align 2 personality i8* undef {
+; CHECK-LABEL: @is_not_42(
+; CHECK-NEXT:  preheader:
+; CHECK-NEXT:    [[BASEPTR1:%.*]] = ptrtoint i8* [[BASEPTR:%.*]] to i64
+; CHECK-NEXT:    [[TMP0:%.*]] = sub i64 0, [[BASEPTR1]]
+; CHECK-NEXT:    [[SCEVGEP:%.*]] = getelementptr i8, i8* inttoptr (i64 42 to i8*), i64 [[TMP0]]
+; CHECK-NEXT:    br label [[HEADER:%.*]]
+; CHECK:       header:
+; CHECK-NEXT:    [[LSR_IV:%.*]] = phi i8* [ [[SCEVGEP2:%.*]], [[LATCH:%.*]] ], [ [[SCEVGEP]], [[PREHEADER:%.*]] ]
+; CHECK-NEXT:    invoke void @maybe_throws()
+; CHECK-NEXT:    to label [[LATCH]] unwind label [[LPAD:%.*]]
+; CHECK:       lpad:
+; CHECK-NEXT:    [[TMP1:%.*]] = landingpad { i8*, i32 }
+; CHECK-NEXT:    catch i8* inttoptr (i64 42 to i8*)
+; CHECK-NEXT:    [[PTR_IS_NOT_42:%.*]] = icmp ne i8* [[LSR_IV]], null
+; CHECK-NEXT:    call void @use1(i1 [[PTR_IS_NOT_42]])
+; CHECK-NEXT:    ret void
+; CHECK:       latch:
+; CHECK-NEXT:    [[SCEVGEP2]] = getelementptr i8, i8* [[LSR_IV]], i64 -1
+; CHECK-NEXT:    br label [[HEADER]]
+;
+preheader:
+  br label %header
+
+header:
+  %ptr = phi i8* [ %incptr, %latch ], [ %baseptr, %preheader ]
+  invoke void @maybe_throws() to label %latch unwind label %lpad
+
+lpad:
+  landingpad { i8*, i32 } catch i8* inttoptr (i64 42 to i8*)
+  %ptr_is_not_42 = icmp ne i8* %ptr, inttoptr (i64 42 to i8*)
+  call void @use1(i1 %ptr_is_not_42)
+  ret void
+
+latch:
+  %incptr = getelementptr inbounds i8, i8* %ptr, i64 1
+  br label %header
+}