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[SPARC] Use the correct register set for the "r" asm constraint. 

64bit mode must use 64bit registers, otherwise assumptions about the top
half of the registers are made. Problem found by Takeshi Nakayama in
NetBSD.

llvm-svn: 358998
This commit is contained in:
Joerg Sonnenberger 2019-04-23 15:15:33 +00:00
parent a2470a4653
commit 6e7cc49d5c
2 changed files with 12 additions and 0 deletions
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2
llvm/lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -3258,6 +3258,8 @@ SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
case 'r':
if (VT == MVT::v2i32)
return std::make_pair(0U, &SP::IntPairRegClass);
else if (Subtarget->is64Bit())
return std::make_pair(0U, &SP::I64RegsRegClass);
else
return std::make_pair(0U, &SP::IntRegsRegClass);
case 'f':

10
llvm/test/CodeGen/SPARC/reg64.ll Normal file
View File

@ -0,0 +1,10 @@
; RUN: llc < %s -march=sparcv9 | FileCheck %s
define dso_local zeroext i32 @f() local_unnamed_addr {
entry:
%0 = tail call i64 asm "", "=r"()
%shr = lshr i64 %0, 32
%conv = trunc i64 %shr to i32
ret i32 %conv
}
; CHECK: srlx